If you took notice of the pun in the title of this column, it was intended. I frequently see attempts to frame discussions of analog design from a digital perspective, a view in which Boolean logic reduces the world to ones and zeros. Such a discussion took place at the DesignCon 2012 on January 31, where a panel of EDA and semiconductor representatives was asked to address the question, “Is it time for an analog comeback?” The question implies that analog design has somehow fallen behind, but outside of the conference room before the session started, some of my fellow analog veterans and I were asking, “comeback from what?”
The DesignCon panel agreed that analog EDA tools and methodologies may not have changed as much as digital, but I recall having exactly the same discussion 15 years ago. Back then I was just joining an EDA startup where our lofty mission was to bring the greatest innovation in digital methodology – automated circuit synthesis – to the world of analog design. We failed for many reasons, not the least of which was failing to ask what the problem was before we prescribed a solution. Looking at analog with a digital measuring stick is a mistake.
Some of the factors that may cloud the perception of the “digerati” can be gleaned from the Analog Subcommittee Chairs’ comments regarding the forthcoming International Solid State Circuits Conference (ISSCC). In the press kit description for the session “Analog Techniques,” the authors introduce their topic with the statement that “Analog technology continues to defy simple categories.” Advances in analog can’t be summed up simply by invoking Moore’s Law and a doubling of transistor density every two years, but they have continued at a similarly rapid pace and are no less impressive. Some might even say they are more so, but that could betray an analog bias (oh, another pun!).
Defying logic by exploiting it
With the focus shifted from tools to actual analog design, DesignCon panelists such as Harold Joseph, Marketing Director for Programmable Systems on a Chip (PSoC) at Cypress Semiconductor, provided several examples for how analog design has advanced to the point where functions that were previously available only in discrete devices are now being integrated into SoCs. Joseph pointed out that high-performance 16-bit Analog-to-Digital Converters (ADCs) with 1-bit linearity are now available on-chip with a microcontroller (MCU).
Panelist Navraj Nandra, Senior Director of Marketing for Analog/Mixed Signal IP at Synopsys, provided some hard data as a reference point on the pace of analog innovation. He compared a 10-bit pipelined ADC from 12 years ago to the same architecture ADC fabricated in a 28 nm process today. The 2012 version is 3.5x faster, 9.5x smaller, and consumes 11x less power than its predecessor. Engineers are challenged by more restricted design rules, said Nandra, but they have also developed new techniques that use digital functions to tune their circuits, overcoming the poorer analog characteristics of scaled transistors while simultaneously boosting performance. Analog designers have defied logic by exploiting it in their circuits.
Analog design breakthroughs to be presented at ISSCC
Attendees at ISSCC (February 19-23) will find advances in analog across a spectrum of applications from DC voltage references to 60 GHz RF circuits, with chips being fabricated in processes scaled as small as 22 nm CMOS to organic semiconductors with 1,000x larger 20 μm transistors. The use of organic transistors in wearable electronics will be a highlight of the ISSCC paper “Insole Pedometer With Piezoelectric Energy Harvester and 2V Organic Digital and Analog Circuits,” and in the session “Innovative Circuits in Emerging Technology,” presented by researchers from the University of Tokyo; the Max Planck Institute for Solid State Research in Stuttgart, Germany; and the Japan Science and Technology Agency on Exploratory Research for Advanced Technology (ERATO).
On the opposite end of the scaling spectrum at ISSCC, Intel will describe the use of bipolar transistors in their new 22 nm FinFET process in the presentation “Ratiometric BJT-Based Thermal Sensor in 32 nm and 22 nm Technologies” on the 21st. According to the organizers of the session on Sensors and Micro-Electro-Mechanical Systems (MEMS), the thermal sensors are not just some of the smallest ever reported, but their 10-to-100 μs conversion times make them fast enough for use as hot-spot monitors in multicore microprocessors.
Demonstrating breakthroughs in RF design at ISSCC, engineers from Sony and the Tokyo Institute of Technology will present how they combined an RF front-end IC 65 nm CMOS chip with a 40 nm CMOS baseband IC to create the first complete 60 GHz CMOS transceiver. Groups such as the IEEE, with the development of 802.11ad Wi-Fi, are looking to utilize the bandwidth of the unlicensed 60 GHz band for short-distance, high-speed wireless transmission of high-definition video, a potential replacement for HDMI cables.
No end to the analog-digital divide
Discussions such as the one that took place at DesignCon will probably never end, as analog and digital design have evolved in such different ways, even into separate IC design disciplines. Few practitioners can remember when all IC design was circuit design, though the most advanced digital chips still rely on such skills.
But there is a critical factor that tends to get ignored in such discussions. Every step along the way of Moore’s Law starts with transistor engineering, which is fundamentally analog. This is followed by gate-level or memory cell circuit design and characterization, also analog. Now analog designers are also reaping the benefits of Moore’s Law through the ability to integrate advanced digital functions that compensate for much less than ideal transistors. It’s time to realize that both design disciplines have advanced together, and neither needs to “make a comeback.”
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