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Approaches and tools for FPGA mixed-signal integration

Allan Chin, Stellamar — Tue, 06 Dec 2011 15:00:00 +0000

As FPGAs become more popular in the electronic design community, the approaches and tools used to integrate analog functions such as ADCs with these digital chips must be refined. Customer demand for high reliability, small footprint, and low power means that engineers have few choices and must look outside the box in their approach to mixed-signal integration with FPGAs.

FPGAs have exploded in popularity in recent years due to their relative low cost and high performance for digital signal processing tasks. The advantages of digital processing, reprogrammability, and variable cost structure have fueled this fast growth. Ironically, as the world has gone “digital,” demand for analog chips and components to grab continuous, real-world data has also risen quickly. As the breakeven unit decision between FPGA and ASIC continues to narrow, one large challenge continues to exist: For the FPGA market to continue growing, digital engineers need robust tools and effective solutions to integrate mixed-signal functions in their digital designs.

Three approaches generally exist for integrating Analog to Digital Converters (ADCs) with FPGAs: external off-the-shelf components, “mixed-signal” FPGAs, and digital ADC implementation. The traditional approach is to add off-the-shelf external ADC components. FPGA manufacturers responded to market demand for analog functionality by introducing “mixed-signal” FPGAs with ADCs in the packaged device. These mixed-signal FPGAs have significant advantages and a few drawbacks (really, when do we engineers ever get exactly what we want?). A third approach, which can fill in the gaps for many applications, is to use a digital ADC IP core to implement ADC functionality directly in the digital fabric of an FPGA. All three approaches are significantly different and require different flows and tools for effective integration.

The external components approach

The traditional integration of ADCs with FPGAs requires external parts. The process involves sourcing and selecting the proper component from an analog parts vendor and understanding how that component will affect size and power budgets. Tradeoffs exist between size, power, and performance. For many applications where size and power are not an issue, this approach works very well. Mixing and matching parts can be an easy way to meet cost budgets for projects that do not require strict optimization. Additionally, for very-low-volume applications, this may be the best approach as many simple ADCs are low cost. However, with the drive to low-power, portable, and high-reliability electronics in consumer, military, medical, and aerospace applications, there is room for improvement. In these markets any external connection point is a possible point of failure, so decreasing external part count would be very valuable. Lastly, for these same markets, system certification or recertification is an issue due to possible discontinuation of a part by a vendor. Certification requires significant resources to be achieved, and is easiest if done only once. In space exploration, this can be of particular concern.

Tools for external part verification

Verification at the PCB level can be divided into two arenas: small designs below 50 MHz operation and complex designs above 50 MHz. Smaller designs below 50 MHz can be verified using interface timing diagrams and a scope. The higher-speed designs require simulation tools such as HyperLynx[1] from Mentor Graphics, which is capable of board-level verification, signal integrity, and other features. Like all simulators, board-level simulators also require good models. Most ADC part vendors provide models with their semiconductor devices. However, when an FPGA design is involved it takes additional time and resources to generate the cycle equivalent model(s) for the FPGA to support PCB simulation. No matter the size, speed, or complexity of the PCB design, using a CAD tool like HyperLynx will verify and validate signal integrity and ensure faster design times.

The “mixed-signal” approach

FPGA vendors have done a good job of responding to the market’s need for ADC inte-gration. Xilinx and Microsemi have great approaches to covering the broad market. By placing one or two 500 KSps or 1 MSps ADCs in the package most applications are covered. These packages are more reliable than the external components approach, and have a smaller overall footprint. These mixed-signal FPGAs naturally command a price premium over other FPGA families for providing packaged ADC functionality. Depending on the product strategy and cost structure, the price premium may be well worth paying. For instance, if the product strategy is to constantly lead in terms of performance, it probably also commands a price premium, and the unit costs may not be that big of a deal. On the flip side, if it has a “continuous cost cutting” strategy, living with this approach may be required until needs can be met more adequately.

Customization is not much of an option in this approach. ADC resolution, sample speed, and number of channels are generally fixed by the vendor. This allows FPGA vendors to support a large swath of the market, but may come at the expense of the power budget. For example, running a voltage measurement at 1 MSps is like using a sledgehammer to drive the head of a pin. The extra speed will negatively impact the power budget. Complex designs these days can require upwards of 48 measurement channels. With mixed-signal FPGAs, adding external analog multiplexers or more mixed-signal FPGAs is the only solution to accommodate the number of channels.

Mixed-signal FPGA simulation and verification tools

Currently, FPGA tools for true mixed-signal simulations are not available. ModelSim[2], however, does support mixed languages such as Verilog, VHDL, and Verilog-A. Depending on the complexity of the analog portion of the design, ModelSim can be used to validate functionality at the mixed-RTL level. A mixed-signal simulator should be used to determine analog performance. However, to determine actual performance a true mixed-signal simulator should be used, such as Mentor ADMS[3] or Cadence AMS[4]. They will also require accurate SPICE models to determine performance, which might be difficult to obtain. Both methods take simulation time or functionality, and more simulation time to determine actual performance.

Digital implementation approach

Some “analog” functions can also be im-plemented using only the digital fabric of an FPGA or ASIC. A crude scheme can be worked up by using an LVDS and small set of resistors and capacitors (Figure 1). Several white papers from Xilinx, Lattice, and others exist on the topic. These papers show resolutions of only 8-9 bits while requiring very high clocks to achieve that performance. Additionally, error rates have been shown upwards of 15 percent.

Figure 1: Some analog functions can be implemented using an FPGA or ASIC digital fabric, shown here using an LVDS and a small set of resistors and capacitors.

External ADCs are unnecessary because a digital ADC is embedded in the FPGA fabric. The removal of external parts lowers board space, and the digital architecture and slower clocks lower power consumption over a comparable analog ADC. Testing is made easy by using the digital test methodology available from any FPGA vendor. These cores can be made rad hard/tolerant by using a rad-hard-tolerant FPGA.

Despite these many advantages, the generic digital ADC technique is severely limited in resolution and bandwidth. This approach will generally not work for applications requiring MHz bandwidths, such as RF communication, as those bandwidths are much more difficult to achieve with digital resources. Here, the external parts approach and perhaps the mixed-signal FPGA approach hold the advantage for those applications.

Through proprietary signal processing, Stellamar can achieve digital ADC performance upwards of 14-bit resolutions and 100 kHz bandwidth with error rates of less than 1 percent and no temperature drift. This method works for applications spanning DC measurements, temperature, touch, acceleration, motor control, audio, and some optical networking tasks. Stellamar works with Xilinx and Microsemi to provide Digital ADC IP cores to engineering teams that require a customized combination of low power, small size, and high reliability, and currently works with aerospace companies on satellite builds and with consumer electronics companies looking to reduce part count to lower cost and increase reliability.

Tools for digital simulation

Current FPGA tools are quite adequate to perform all digital simulation with an embedded digital ADC. This provides a level of certainty at the RTL and gate levels to the entire design before configuring an FPGA. This verification and validation is achieved by using any Verilog simulator supplied with the standard FPGA toolkit, which is ModelSim in most cases. Since a digital ADC is described in Verilog or VHDL, any FPGA can be targeted without the need for additional models other than the supplied FPGA digital library. With the added flexibility of reprogramming and the availability of different-sized FPGAs, designers can optimize not only the system by defining the exact ADC requirements, but also the power and board. A typical FPGA design flow starts with the instantiation of the digital ADC IP into the design. Then the entire design is synthesized to the FGPA gates using the tool provided with the FPGA toolkit. Post-place and route gate level timing simulation is usually performed with the provided ModelSim simulator to perform an all-digital simulation. This validates the gate level implementation of a mixed-signal design without the need of a mixed-signal simulator.

Reintegrating analog and digital

The growth of the FPGA market for high-reliability and low-power applications hinges on better integration of “analog” with “digital.” Three approaches for implementing ADCs with FPGAs are available. External components can be easy to use but occupy more board space. Mixed-signal FPGAs are easily accessible and offer great performance, but are technology-dependent, more expensive than standard FPGAs, and are limited in array size. Embedded Digital ADC cores are technology-independent and offer a migration path to ASICs, use digital testing, and are optimized for size and power; their main drawback is a limitation on bandwidth.

From a system perspective, the mixed-signal FPGAs and embedded Digital ADCs are best for systems that require certification, such as medical, consumer, and military devices, as they remove the possibility of a system change due to end-of-life of an external ADC.

Good mixed signal integration starts with understanding what signals are being measured and what is required to measure those signals. Once requirements are accurately established, an approach can be selected. No matter which method is used, a PCB simulation should be run at the board level in all cases. The ability to use a Digital ADC core can simplify the design integration and validation of an FPGA-based mixed-signal design.

Each approach and tool set have real value to the engineering team, but each have their drawbacks. Looking to the future, more analog functions such as power management and clocking will be able to take advantage of digital tool sets for modeling and testing.

References

Mentor Graphics HyperLynx: http://www.mentor.com/products/pcb-system-design/circuit-simulation/hyperlynx-signal-integrity/
ModelSim: http://model.com/
Mentor Graphics Mentor ADMS: http://www.mentor.com/products/ic_nanometer_design/events/adms_mixed_signal_workshop
Cadence AMS: http://www.cadence.com/products/pcb/ams_simulator/pages/default.aspx

Allan Chin is CEO at Stellamar and has more than 30 years of design experience with high-performance digital and mixed-signal systems. His broad expertise covers many areas of IC design, including system requirement definition, chip development, mixed-signal simulation, verification, prototyping, and lab testing. Allan has a B.S. in Electrical Engineering from Marquette University, Milwaukee, Wis., and holds nine patents. Allan can be reached at allan.chin@stellamar.com

Stellamar info@stellamar.com www.stellamar.com

Hot Chips will need more analog to support multicore

Mike Demler, EE Daily News — Thu, 10 Nov 2011 15:00:00 +0000

A common thread that ran through the 23rd Hot Chips conference presentations was the integration of more complex and higher performance analog circuits as an absolute requirement.

Conexant adds Keterex audio playback IC to launch new product line

Mike Demler, EE Daily News — Thu, 10 Nov 2011 15:00:00 +0000

Conexant has announced the launch of a new audio playback product line acquired from Keterex to play 8 KHz audio data directly to an external speaker via an on-chip digital audio processor and class-D amplifier.

National Semiconductor adds 16-bit and 24-bit sensor analog front ends

Mike Demler, EE Daily News — Thu, 10 Nov 2011 15:00:00 +0000

National Semiconductor Corp. has announced the availability of seven new 24-bit and 16-bit multi-channel sensor AFEs (analog front-ends) to enable designers to easilly configure signal paths from interface sensors to microcontrollers.

EE Daily News 20-page special report reviews the EDA/IP exec panel at GTC2011

Mike Demler, EE Daily News — Thu, 10 Nov 2011 15:00:00 +0000

The 2nd annual GLOBALFOUNDRIES Technology Conference (GTC) provided a rare opportunity to hear industry leaders discuss a wide range of issues that will impact the future direction of the electronics design ecosystem.

TI claims industry’s lowest power for NFC transceiver

Mike Demler, EE Daily News — Thu, 10 Nov 2011 15:00:00 +0000

TI is targeting its new NFC transceiver at infrastructure devices which communicate to NFC-enabled devices such as smartphones.

Designing rugged, multifunctional HPA controllers to prevent system damage

Mario Razo, db Control — Fri, 02 Sep 2011 15:00:00 +0000

High Power Amplifiers (HPAs) are critical in microwave systems commonly found in Electronic Countermeasures (ECM), Electronic Warfare (EW) simulators, radar, and communications links used by the military. Unfortunately, integral Vacuum Electron Device (VED) requirements introduce hostile environments for HPAs. However, a rugged, multifunctional, microcontroller FPGA-based controller can solve this challenge. (U.S. Navy photo by Mass Communication Specialist 3rd Class Dylan McCord)

High Power Amplifiers (HPAs) are the backbone of most microwave systems used for military applications such as radar, Electronic Countermeasures (ECM), communication systems, and Electronic Warfare (EW) simulators. HPAs using Traveling Wave Tubes (TWTs) come in two categories. Both versions use Vacuum Electron Devices (VEDs), TWTs, Klystrons, and Gyrotrons to amplify the modulated RF waveforms given at the input to the desired power level before feeding to the radiating element.

The difference is that one version of the HPA is the microwave power amplifier with all RF input and output parts, power amplifying TWT (or other VEDs), digital interface and protection circuits, and the power supply all integrated into one assembly. The other version is the compact Microwave Power Module (MPM), which uses a miniature version of the TWT and a solid-state driver amplifier integrated with a densely packaged power supply (Sidebar 1). Being a very compact module, the MPM does not have all functions within the assembly and can produce RF power in the range of about 100 W CW or 1,000 W peak pulse power. The VEDs require high operating voltages of 5 to 25 kVdc and proper switching sequences and protection circuits.

Sidebar 1: An inside look: How microwave systems solve high-power electronic attacks

(click graphic to zoom)

To keep the HPA controller functioning is vital for continued effective systems operation. Thus, to prevent damage to costly parts and the system, ongoing monitoring and status indication of every critical parameter are essential. For example, HPA controllers must monitor HPA health by measuring critical parameters such as the cathode voltage, current, body temperature, and so on. Controllers must also provide protection to prevent damage, in addition to offering interface between the HPA and host system, executing housekeeping functions, and functioning as the Built-In Test (BIT) system for the HPA.

In addition, HPA controllers must be able to withstand a “hostile” environment, as they reside in an area of the system where they can be subjected to high voltages up to 25 kVdc, high-energy switching up to 10 Joules, and other severe operational stresses such as extreme temperatures (-55 °C to +125 °C) and high vibration levels of up to 20 G rms. This is further complicated by the high levels of switching currents in the order of 100 A per microsecond and short-circuit currents of thousands of Amps. If such currents were to be going through any of the VEDs, it will destroy these expensive devices beyond repair.

The design challenge is to provide suitable protection and integrate BIT functionality and continuous monitoring into a microcontroller FPGA-based embedded controller because of the HPA’s “hostile” environment. Design engineers must consider the “hostile” environment factors prior to establishing the appropriate architecture for HPA embedded controllers. Figure 1 illustrates a basic HPA system architecture. Three major modules form an HPA system: a VED, a controller, and a high-voltage power supply that provides the required voltages to different elements of the VED such as the heater, cathode, collectors, and the electron beam. The HPA controller offers control and protection for the entire system.

Figure 1: The basic HPA system includes a VED, power supply, and HPA controller.

(click graphic to zoom by 1.9x)

Protecting HPA systems’ critical components

Every HPA system requires control and protection circuitry to protect the VED and other critical system components from adverse conditions and possible failures that could lead to major system damage and considerable economic impact. There are several factors to consider when designing high-performance HPA embedded controllers. For example, the high operating voltages (5-25 kVdc) required by an HPA system can cause severe damage to sensitive components such as microprocessors, microcontrollers, FPGAs, memory devices, Analog-to-Digital Converters (ADCs), and other critical components. Extreme protection is required to keep these devices safe and active under any circumstance, especially when high voltage and switching current spikes occur. Current spikes of HPA systems can vary from a few Amps peak up to hundreds of Amps peak, depending on the VEDs’ requirements.

The hostile environment surrounding the embedded controller can also cause false alarm failures or unexpected behavior. Switching noise produced by the power supply switchers can produce extremely sharp noise spikes of nanoseconds duration, which can occupy more than a few MHz of bandwidth. These can corrupt critical signals of the HPA system such as Serial Peripheral Interface (SPI), Inter-Integrated Circuit (I2C), and serial data lines.

The HPAs need to meet various conditions such as time delay required by VEDs (180 seconds typical), operate command from the host interface, and Focus Electrode (FE)/grid enable and beam control (-1100 Vdc to +500 Vdc) prior to amplifying any given RF input signal of 2 to 40 GHz. The HPA controller must keep control over these signals and execute the commands in the right sequence under any condition to assure safety and proper functionality of the HPA system. Improper switching sequence of these signals could damage the VEDs, accidentally transmit RF output power (in some cases 10 kW peak), or harm personnel. Implementation of control signals with safe-state configuration is necessary to achieve a suitable and safe HPA controller. Safe-state signals will protect the VEDs from being active during initial power-up, standby, or when transmission is not desired. The integration of microcontrollers and FPGAs into HPA controllers empowers HPA systems by providing high-performance protection and extensive functionality, as will be discussed later.

“Universal” controllers satisfy next-gen systems

Modern mission-critical systems require HPAs that meet all performance requirements, provide 100 percent availability for the mission duration, and act as multifunctional HPA controllers capable of withstanding high-stress environments while effectively performing essential functions. A high-performance “universal” HPA embedded controller with an input power of +15 Vdc, 5 W, and dimensions of 6.0" x 2.5" x 0.90" can meet these requirements for next-generation military airborne systems. Figure 2 depicts its basic block diagram and hardware architecture.

Figure 2: Multifunctional embedded HPA controller powered by an FPGA and a microcontroller

(click graphic to zoom by 1.9x)

The main function of this embedded HPA controller is to protect the critical elements of the system by monitoring the diverse parameters of VEDs such as Helix current up to 600 mA, cathode voltage from 5 kV to 25 kV, over-temperature (typical 125 ºC), and output reflective power up to 100 W average. These parameters vary from VED to VED, and the embedded controller offers flexible protection limits. It also monitors other critical parameters of the HPA such as input current, input voltage, and temperature of the high-voltage power supply. Additionally, the controller provides built-in test features through different serial communication protocols such as RS-422, RS-485, or RS-232. This function enables the host interface to continuously retrieve (automatically or upon request) the HPA system’s status. The HPA controller provides status between 1 and 2 seconds after application of power.

The embedded HPA controller can receive commands such as Model Identification Query, Status Query, Operate, and Stand-by, for example, from the host interface via the serial interface and execute these commands almost immediately (in less than 20 ms) after reception and acknowledgement.

Using a microcontroller, FPGA to protect the HPA

The microcontroller and FPGA components are the main core of the embedded HPA controller that protects the EW, ECM, radar, or other military system electronics from damage; these controllers perform the majority of the tasks with aid from the protection circuitry section and other miscellaneous devices, as follows:

The main functions of the microcontroller are overall supervision, host communication, self-test, and technician assistance features via RS-232. The microcontroller also verifies board/system configuration, communication with a remote panel, and communication with other controllers, and conducts periodic verification of FPGA configuration to guard against single-event troubles.
The protection circuitry continuously monitors the HPA system’s critical parameters by collecting feedback from various HPA elements. Such feedback could be temperature readings (-55 °C to 150 °C), cathode voltage, helix current, reflected output power from the VED, input under-voltage, and more. The input gate signal (pulse systems only) is detected by a pulse measurement function inside the FPGA to protect the VED from over-duty of 3 to 30 percent, over-pulse width of 2 µs to 300µs, and over-frequency of 200 Hz to 100 KHz. The protection circuitry also incorporates a high-speed pulse capture that accepts RF detector signals. These signals are conditioned, scaled, and digitalized, and the FPGA transmits the digitalized values through the serial interface.

The FPGA enhances the HPA controller by providing an extensive set of features to make it more robust and multifunctional. The FPGA architecture includes configurable functions via tailored logic loads, polarity, and mask registers to allow a common logic load for multiple HPA systems.

The FPGA provides control of a 12-bit ADC and compares configurable thresholds against digitized voltage inputs such as cathode voltage (scaled down from 5-25 kV to less than 10 Vdc) and detected RF output power (-80mV) from the VEDs (typically amplified and inverted from -80 mV to +10 Vdc). Additionally, the FPGA captures and analyzes digitized data, performs gate-pulse measurements (2-300 µs with frequencies up to 100 KHz), and provides voltage-to-power conversion using a lookup table, in addition to peak detection.

As a safety feature, the FPGA is configured to keep the I/O signals in safe-state; the microcontroller is capable of detecting any FPGA malfunction on the next polling cycle and taking appropriate action.

HPA controllers for today’s military systems

While HPAs are essential in most microwave systems used for military applications such as ECM, radar, communication, and Electronic Warfare simulators, it can be challenging to integrate the necessary protective functions into the HPA’s embedded controller. The hostile environment introduced by HPA systems because of the VED’s requirements is inevitable, and it compromises the integrity of HPA embedded controllers. Design engineers are obligated to live with this matter and must protect the embedded controller. dB Control has developed such an embedded HPA controller, which is microcontroller FPGA-based, noise immune, multifunctional, and firmware configurable, minimizing the need for design changes and harnessing FPGAs’ and microcontrollers’ high performance and extensive functionality to protect the system.

Mario Razo is a Design Engineer at dB Control, working with high-power amplifiers and microwave power modules for military and commercial customers. Email him at mrazo@dbcontrol.com.

Meppalli Shandas is dB Control’s VP of Technology and Business Development. He has 40 years of design experience with microwave hardware for Electronic Warfare, radar, and communication systems. Email him at mshandas@dbcontrol.com.

dB Control 510-656-2325 www.dBControl.com

Embedding flexible analog interface IP into digital SoCs

Manuel Mota, Synopsys — Fri, 12 Nov 2010 15:00:00 +0000

More and more analog and mixed-signal capability is being integrated into Systems-on-Chip, including baseband RF functions. Careful attention to detail is needed to maintain circuit performance and deliver functionality while keeping power consumption low. Designers can explore the criteria for a flexible analog interface to build a successful wireless communications device.

Today’s consumers are getting more and more sophisticated. They are now creators of their own content, like HDTV videos or large sets of digital photographs. They expect to be able to share it anytime, anywhere, with anybody, and without delay; they do not want to be limited by slow wired connections.

These consumers are driving the implementation of broadband wireless network terminals in every conceivable device, beyond the traditional mobile phone and into the PC, TV, car, camcorder, and even picture frames.

To serve this consumer expectation, terminal devices must be cost-effective and simple to use. In addition, the wireless transceiver in these devices should be compatible with all broadband communication standards, including Long-Term Evolution (LTE), WiMAX, and Wi-Fi. These goals can be achieved by carefully defining the analog interface’s characteristics and internal components, paying attention to several details.

The wireless baseband analog interface

A traditional communications system (Figure 1) comprises an analog RF block to translate over-the-air communication into baseband (BB) analog signals and a digital BB processor block to translate modulated signals into meaningful communication content. A wireless BB analog interface translates signals between the analog and digital domains.

Figure 1: An analog interface connects the analog RF block and digital baseband processor block in a broadband communications transceiver system.

(click graphic to zoom by 1.5x)

To implement interchip communication between the digital System-on-Chip (SoC) with an external RF chip (RFIC), the analog interface is typically integrated with the digital BB processor in a complex digital SoC.

The analog interface comprises an IQ-Analog-to-Digital Converter (ADC) in the receive path and an IQ-Digital-to-Analog Converter (DAC) in the transmit path. It also includes an auxiliary ADC and an auxiliary DAC for measurement and control purposes. A Phase-Lock-Loop (PLL), which generates the sampling clock for all these converters, can also be considered part of the interface.

Most modern implementations of wireless communications transceivers are multi-antenna array (Multiple In, Multiple Out or MIMO). In these cases, the receive and transmit paths use multiple instantiations of an IQ-ADC and IQ-DAC (one per antenna). These architectures implement advanced processing techniques such as diversity or special multiplexing to improve communication quality.

Embedding a flexible analog interface into a digital SoC

To implement multiple communication standards and enable the BB chip to be used with any RFIC, the analog interface must be very flexible. The definition of the interface and the internal data converters should take this into account to facilitate the analog interface’s integration inside the digital SoC. The following ground rules should be followed:

The interface should be compatible with multiple wireless communication standards while keeping power dissipation at a minimum.
The interface should be flexible, allowing seamless connection between the BB chip and any external RFIC without requiring additional external circuitry.

The system designer should thus look beyond the basic characteristics of a data converter IP (area, power dissipation, throughput, dynamic range) and into the detailed characteristics that make it flexible and easy to integrate.

Compatibility with multiple standards

It is interesting to observe that most broadband wireless communication standards have defined a similar set of performance characteristics for the analog interface. In fact, most protocols define a maximum communication channel width at 20 MHz (or 40 MHz for Wi-Fi 802.11n). Furthermore, the conversion resolution required is typically 10- or 12-bit. This means a data converter with these characteristics is effectively compatible with multiple protocols. However, the optimal sampling rate for different communication modes within the same protocol (LTE mode 1 or mode 6, for example) may differ.

The communications system should be configured such that the same hardware can be used in all modes in the most power-efficient way. For the data converters in the analog interface, this means they should allow operation at a wide range of sampling rates without performance variation. Furthermore, operation at low sampling rates should not penalize the system’s energy efficiency; the converter’s power dissipation should be proportional to the sampling rate while maintaining performance, as shown in Figure 2.

Figure 2: For optimal implementation of the analog interface, the power dissipation scales proportionally with sampling rate while maintaining consistent performance.

(click graphic to zoom by 1.9x)

Optimal interface with the RFIC (ADC/DAC)

For the highest system flexibility, the BB processor chip should be implemented in a way that does not impose restrictions on the RFIC connected to it.

Systems are typically implemented using a DC-coupled zero IF demodulation scheme. The analog signal level coming out of the RF block is not known and varies for different vendors.

To communicate seamlessly with all RFICs, the data converters in the analog interface need to support a wide range of input signal common mode voltages and perform the signal-level translation in its internal signaling levels without the need for extra external components (coupling capacitors or operational amplifiers).

For the receive path, dedicated level-shifting circuitry in the ADC sample and hold can implement all these functions and thus guarantee maximum interface flexibility. Figure 3 shows an example of an ADC input stage that can process signals with a wide range of common mode levels.

Figure 3: An ADC input stage implementation compatible with all common RFIC signal levels can process signals with a wide range of common mode levels.

(click graphic to zoom by 1.9x)

In the transmit path, a DAC using a current steering architecture enables the level translation function to be implemented without further overhead.

It is possible to alleviate the complexity of the analog reconstruction filter and thus simplify the RF block by using the transmit DAC at a higher sampling rate to increase signal oversampling. However, this solution is only viable if the DAC’s power dissipation and performance are not affected by the higher sampling rate.

Support for 2G/3G/4G communications

A special category of wireless communication modems must support communications based on protocols for multiple generations (2G, 3G, and 4G), such as in the context of cellular applications. Modems for cellular applications must implement widely different requirements using the same hardware, for example:

Narrowband Gaussian-filtered Minimum Shift Keying (GMSK) with 200 kHz channel bandwidth requires ADC performance in excess of 74 dB Signal to Noise and Distortion Ratio (SNDR).
Broadband LTE with up to 20 MHz channel bandwidth requires ADC performance in excess of 63 dB SNDR.

The optimal solution for these modems is to implement the ADC using a wideband sigma-delta architecture. These converters are designed using a highly programmable analog sigma-delta modulator, followed by programmable digital filters. This embedded programmability allows trading off speed (signal bandwidth) and dynamic range (SNDR) while maintaining the power dissipation at a minimum. Additionally, due to the high oversampling rate, the analog anti-aliasing filters present in the RF block can be simplified.

Processing large bandwidth analog signals

The most common demodulation technique used for broadband wireless communications is based on a zero/near-zero IF implementation. However, in some cases, IF demodulation is preferred. In these situations, the IF signal is digitized and processed directly in the digital domain, thus simplifying the analog RF circuitry. In IF demodulation, the communication channel band to be digitized by the ADC is centered on a high frequency (the IF frequency).

To digitize these signals, the ADC input must be able to sample high-frequency signals while not jeopardizing the ADC’s performance. Traditional converters for baseband applications exhibit performance degradation for high-frequency input signals. An ADC that integrates a dedicated high-frequency input stage targeting high-frequency signals can overcome this limitation (see Figure 4).

Figure 4: Processing high-frequency input signals can impede the performance of ADCs unless they integrate a dedicated high-frequency input stage.

(click graphic to zoom by 1.9x)

Ready-to-integrate IP

Achieving a successful design that integrates broadband wireless communications interfaces in a digital SoC depends on the definition of the analog interface and a careful selection of the blocks that make up the interface. Selection should look beyond the common criteria of resolution/performance and take into account the features embedded in these converters that help build a flexible solution. These converters should seamlessly communicate with any RFIC and accommodate all common broadband communication standards in the most power-effective way using the same hardware.

Synopsys DesignWare Data Converters were created in view of such needs. Synposys offers a complete portfolio of analog interface solutions that greatly simplifies its integration in a digital BB processor SoC.

For more information on the Synopsys DesignWare Analog IP Data Converters portfolio, visit www.synopsys.com/IP/AnalogIP/DataConversion/Pages/default.aspx.

Manuel Mota is technical marketing manager for data converter IP within the Solutions Group at Synopsys. He has worked in the semiconductor industry for more than eight years as analog IP designer and business developer for data conversion products at Chipidea Microelectronica. Manuel holds a PhD in Electronic Engineering from Lisbon Technical University, which he completed while working at CERN as a Research Fellow.

Synopsys 650-584-5000 manuel.mota@synopsys.com www.synopsys.com

MCUs power energy-efficient apps

Ganesh Moorthy, Microchip Technology — Tue, 15 Dec 2009 15:00:00 +0000

ECD: What’s the primary focus right now in your strategy to develop microcontrollers for embedded devices?

MOORTHY: We have a series of initiatives. Microchip’s eXtreme Low Power (XLP) technology initiative is delivering an array of new products enabling world-leading battery life in embedded products, as well as low energy consumption consistent with a broad range of green regulations. For example, our 8- and 16-bit PIC microcontrollers with XLP technology have the world’s lowest sleep currents, down to 20 nA, which enables battery life of up to 20 years. (Figure 1 shows the Microchip PIC24F16KA family.)

Figure 1: The PIC24F16KA 16-bit family is one example of MCUs that employ XLP technology.

(click graphic to zoom by 1.9x)

We are also continuing to provide the world’s smallest microcontrollers, as we develop and deliver smaller and thinner packages that are critical for portable or space-constrained applications.

Performance is a third area of focus, not only in the traditional sense of the amount of work that the microcontroller can perform in a unit of time, but also in the sense of architectural performance – the amount of software code required to accomplish a given task. Performance in these two dimensions is an important determinant of overall system cost for embedded developers.

Industry-leading analog technology is a fourth area of focus, as microcontrollers absorb complex and highly precise analog functions such as high-performance/high-precision analog-to-digital converters, digital-to-analog converters, operational amplifiers, and other traditionally discrete functions.

ECD: How are you changing your reference design and development kit offerings to meet engineers’ needs?

MOORTHY: As we enable more complex applications, the software content that Microchip either has to provide or ensure exists through our ecosystem partners has grown significantly. To enable embedded engineers to rapidly prototype and validate innovative ideas, we continue to make our development tools easier to use and low cost to try. Yet there is no compromise on the level of capability that our development tools offer compared to much more expensive development tools from other microcontroller manufacturers. The low cost of our development tools combined with the extensive localization we offer help embedded engineers in many emerging economies (where embedded design activity is skyrocketing) to quickly get up and running in developing their innovative applications.

ECD: Given all that, what would you say is the one overriding trend that will reshape the way devices are developed in this new decade?

MOORTHY: There are three interrelated trends that are shaping how embedded devices will be developed. First is the need for greater energy efficiency so that end products meet or exceed the plethora of green regulations and customer preferences that will evolve during the next decade. As solutions enabling improved energy efficiency become more prevalent and available in small packages, it will further meet the customer need for portability; thus, end products will have very long battery life and will be lighter because smaller batteries can be used. Finally, as these highly portable, more energy-efficient end products become available, the need for richer and simpler human interfaces with the devices will become much more important, as device makers seek to build products that end users will find more intuitive to use and more enjoyable to derive value from.

Ganesh Moorthy is the Executive Vice President and Chief Operating Officer of Microchip Technology, Inc., based in Chandler, Arizona. Originally from India, he came to the United States as a student in 1979 and became a U.S. citizen in 1994. Prior to joining Microchip in 2001, he was general manager of Intel’s 8/16/32-bit Microcontroller Division and CEO of Cybercilium, a small software start-up company. He has undergraduate degrees in Physics and Electrical Engineering and an MBA in Marketing.

Microchip Technology

480-792-7200

Ganesh.Moorthy@Microchip.com

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SDR applications: One size does not fit all

Andrew Reddig, TEK Microsystems, Incorporated — Mon, 04 Feb 2008 15:00:00 +0000

Engineers designing modern SDR applications know there are many trade-offs between options, including PMC/XMC versus VXS. As newer FPGA technology is developed and deployed, however, VXS will be better able to satisfy growing requirements for more board and front-panel space, higher densities, more IP core and I/O choices, and improved analog performance than PMCs or XMCs.