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  • 3DSP  (1)
    • HiFi
      An integrated, Web-based design environment that enables users to design DSP SoCs over the Internet (+)

      Features:

      • The user defines the SoC specification, then defines the hardware and software requirements using online design tools available through HiFI (Highly Flexible, Integrated)
      • A cycle-accurate C-simulator of the custom SoC design, an assembler/linker, and a C-compiler for the configured DSP core, plus estimates of SoC die size and performance are provided through the Internet
      • When the design is finalized, RTL (Registered Transfer Level) code ready for synthesis is generated and sent to the user
  • 3L Ltd  (1)
    • Diamond FPGA
      Diamond FPGA builds a single application file by taking DSP and FPGA tasks and automatically combining them with all the necessary support logic (+)

      Features:

      31281.jpg
      • Loading this one file initializes every DSP and FPGA in the system and starts the final application running
      • Hardware/software codesign environment uses VHDL or high-level EDA tools
      • Provides an optimization framework for thread-based functions [...]
  • Advanced Testing Technologies (ATTI)  (1)
    • N/A
      The consulting team at ATTI takes a hands-on approach to consulting, working side-by-side with customers to optimize every facet of an operation (+)

      Features:

      • In addition to consulting, we provide extensive product training and concept education
      • ATTI's services encompass the following areas: integrated logistics, systems hardware design and analysis, acquisition management for competitive programs, CAD/CAM Level III drawing development, configuration and data management, test and evaluation, and documentation [...]
  • ALDEC, Inc  (3)
    • Riviera-PRO
      Riviera-PRO is a common-kernel, mixed language, multi-platform simulator for Verilog, SystemVerilog, VHDL, SystemC/C/C++, Assertions and EDIF (+)

      Features:

      • It supports System Level Verification
      • Languages Supported: VHDL, Verilog HDL, SystemVerilog IEEE 1800 Design, SystemVerilog IEEE 1800 (Verification), SystemC TM 2.2 IEEE 1666/OSCI 2.2, Mixed language & EDIF 200V
      • Supported Platforms: Linux 32-bit, Linux 64-bit, Microsoft Windows, 2000/2003/XP/VISTA
    • ALINT
      ALINT™ is a VHDL and Verilog Design Rule Checking Tool used to analyze HDL source code against a comprehensive set of ASIC design guidelines for early bug detection, cross-probing (+)

      Features:

      • VHDL IEEE 1076 (1987, 1993, 2002 and 2008), Verilog (1995, 2001, 2005) and Mixed Language Design analysis/rule checking
      • STARC® VHDL Rule Library
      • STARC® Verilog Rule Library
    • Active-HDL 8.1 EE
      Active-HDL is a powerful mixed-language simulator with tools for graphical design entry, project management, HDL verification and documentation (+)

      Features:

      • A multi-vendor flow manager control
      • Languages supported: VHDL, Verilog® , SystemVerilog IEEE 1800 Design, SystemC TM 2.2 , Mixed language & EDIF 200V
      • Supported Platforms: Microsoft Windows 2000/2003/XP/VISTA
  • Altera Corporation  (1)
    • Error Correction Cores
      A family of nine high-speed cores built around Altera's new Reed-Solomon Compiler, Viterbi Decoder, and Turbo Encoder/Decoder which are all delivered with Altera's MegaWizard GUI application interface (+)

      Features:

      • Cores can be used to do functional simulation, using VHDL and Verilog simulators
      • A bit-accurate compiled C model is available for system-level simulation to calculate bit error rates
      • Supports data rates in excess of 2 Mbits/sec
  • Altium Limited  (2)
    • Protel
      A complete board-level and FPGA-level design solution in a single application (+)

      Features:

      • Fully supports the design of FPGAs and their integration onto the PCB
      • Based on LiveDesign-enabled DXP platform to provide seamless integration with other Altium design systems
      • Hierarchical, multi-channel schematic editing environment
    • CircuitStudio
      A decdicated universal front-end engineering design tool for both board-level and programmable device design (+)

      Features:

      • Integrates: hierarchical, multi-channel schematic capture, VHDL coding and functional simulation, SPICE 3f5/XSpice simulation, pre-layout signal integrity analysis, and more than 68,000 components (16,000 include simulation models)
      • Comprehensive design error checking
      • Able to define critical PCB data such as board outline, design rules, and component placement
  • Apache Design, Inc., an ANSYS subsidiary  (1)
    • Advanced Low Power Design and Analysis
      Apache Design provides advanced chip-level power analysis, optimization, and sign-off solutions that allow an end-to-end low-power methodology from prototyping to sign-off. Apache's integrated products and methodologies address chip-package-system power and noise challenges and help deliver more power-efficient, high-performance, and noise immune chips for a broad range of end-markets and applications. (+)

      Features:

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      • Predictable single-pass power savings with production-proven RTL power analysis.
      • Early power grid and package prototyping before chip layout is available.
      • Quickly identify few worst case power cycles from millions of RTL vectors for greater power sign-off coverage.
  • Applied Integration  (1)
    • AI-VSD-301
      A microwave detector utilizing zero bias Schottky technology and providing both TTL threshold and analog video outputs (+)

      Features:

      • Input impedance 50 ohm
      • Low-level sensitivity 0.5 mV/W
      • Output capacities 3.0 pf
  • Aptix Corp.  (1)
    • Expedition
      An interactive environment enabling creation of prototypes for system-on-chip (SoC) devices directly from Register Transfer-Level (RTL) designs (+)

      Features:

      • Expedition emulation software, automates the RTL design mapping process allowing users to focus on verifying and debugging SoC designs
      • The package is a front-end tool for Aptix's System Explorer prototyping tools, shich map RTL design descriptions for FPGA logic netlists
      • Simple-to-use graphical user interface built on Java technology
  • ArchPro Design Automation  (1)
    • ArchPro MVSIM
      World's first Electronic Design Automation (EDA) solution for verification of Power Managed Designs (+)

      Features:

      • Supports ARM® Intelligent Energy Manager (IEM) technology
      • MVSIM enables the user to bring any system level architectural decision on voltage scaling into the Register Transfer Level (RTL) and verify it.
      • MVSIM works with mainstream simulators like ModelSim (Mentor Graphics Corp.), NC-Sim (Cadence Design Systems, Inc.) and VCS (Synopsys, Inc.) to verify multiple voltages.
  • AutoESL Design Technologies, Inc.  (1)
    • AutoPilot FPGA: No-compromise High-level Synthesis
      Support for fixed-point and floating-point arithmetic in C, C++ and SystemC (+)

      Features:

      46484.jpg
      • Highest quality of results: delivered performance 35x compared to TI DSP processor on an Optical flow (Video) application
      • Extensive architectural exploration and “what-if” analysis without changing the source
      • Flexible interface synthesis for internal and external interfaces such as memories, FIFOs, buses and interfaces such as AXI
  • Avnet Electronics Marketing  (2)
  • Bluespec Inc.  (1)
    • Bluesim simulator
      Bluesim simulator meant for virtual prototyping and high-speed, source-level simulation and debug. Bluesim accelerates the product development cycle by delivering an accelerated cycle-accurate, transaction-level simulation model from the same electronic system level (ESL) source also used to generate high-quality register transfer level (RTL) code. The combination of Bluesim and Bluespec's ESL synthesis offers a single environment –– what Bluespec refers to as a Virtual Systems Platform –– for modeling and design, creating an automated path to hardware. This virtual prototyping environment is suitable for both software development and modeling, and can be used for unit development and testing, or leveraged for regression testing. Key new features of Bluesim include increased simulation performance, with acceleration ranging from four to 15 times faster than traditional event-based simulators, and a direct C interface that avoids co-simulation overhead. An interactive interface can be employed for user control over debug. And, it supports multiple clock domains enabling the simulation of systems with blocks running at different clock speeds. A native ESL simulator supporting Bluespec SystemVerilog, Bluesim can be used for software drivers, initialization and diagnostics, firmware, micro-code and accurate modeling and design tradeoffs. (+)

      Features:

      • [...]
  • Calypto Design Systems  (1)
    • ESL HW Design and RTL Power Optimization
      Calypto Design Systems leads the industry in technologies for ESL hardware design and RTL power optimization. These technologies empower designers to create high quality and low power electronic systems for today’s most innovative electronic products. (+)

      Features:

      • Catapult lets designers use industry standard ANSI C++ or SystemC to describe functional intent at the ESL level. From these high-level descriptions, Catapult automatically generates production quality RTL to dramatically shorten both design and verification in today’s hardware design flows.
      • PowerPro is an automated RTL power optimization and analysis product that identifies and inserts sequential clock gating and memory enable logic into synthesizable Verilog and VHDL designs. PowerPro has proven to reduce power by up to 60% in RTL designs.
      • SLEC is a sequential equivalence checker that handles differences in design state, timing and levels of abstraction. SLEC enables ESL hardware design by using formal methods to comprehensively proving equivalence between RTL implementations and system-level models. [...]
  • Carbon Design Systems  (1)
    • VSP
      VSP enables early chip and system validation by allowing multiple levels of abstraction to be simulated together including C, SystemC, RTL, IP cores, transaction-level, and instruction-level models. (+)

      Features:

      • VSP models are derived from a chip's RTL specification and have the benefits of drop-in interoperability, high-performance, and hardware-accuracy.
      • VSP software opens new doors for ESL adoption by allowing customers to incorporate IP and legacy RTL into a system simulation early in their design cycle
      • Firmware and the underlying virtual hardware can be validated together before tape-out, rather than waiting for first silicon or spending months to develop an approximate behavioral model [...]
  • Cliosoft, Inc.  (1)
    • SOS Design Data and IP Management
      ClioSoft's SOS Design Data Collaboration Platform is built from the ground up to handle the requirements of hardware design teams. The SOS platform enables global team collaboration, design & IP reuse, and efficient management of design data from concept through tape-out. (+)

      Features:

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      • Version control integrated into design flow
      • Composite object support for cell views
      • Efficient multisite collaboration
  • CoFluent Design  (1)
    • CoFluent methodology for UML
      New UML methodology for modeling and simulating real-time embedded systems and chips (+)

      Features:

      44599.jpg
      • Combines SysML and MARTE profiles, and is supported by the CoFluent Studio software
      • CoFluent Studio is a visual system-level modeling and simulation toolset based on Eclipse that integrates MagicDraw tool to capture UML diagrams; CoFluent Studio allows designers to model real-time embedded applications and use cases, simulate their execution on multiprocessor/multicore platforms, and obtain power and performance data
      • Models are captured in graphical diagrams using standard UML notations or CoFluent optimized domain-specific language (DSL)
  • Elanix, Inc.  (1)
    • HDL Design Studio (HDS)
      Automatic VHDL or Verilog code generation (+)

      Features:

      19190.jpg
      • Bit true, cycle accurate simulation library
      • Automatic detection of overflows and underflows
      • Base-2 histogram generation for word length optimization
  • GateRocket, Inc.  (1)
    • RocketDrive
      RocketDrive is a Device Native FPGA verification system that provides a dramatic increase in FPGA verification accuracy,throughput and debugging productivity (+)

      Features:

      42692.jpg
      • Replaces RTL and gate-level simulation models with actual FPGA hardware for Device Native simulation
      • Accelerates verification throughput by up to 10x or more over RTL simulation
      • Identifies problems with IP blocks, pin-outs and tool chain anomalies that are missed in normal simulation
  • GLOBALFOUNDRIES  (1)
    • GLOBALFOUNDRIES Services
      GLOBALFOUNDRIES, one of the world's top three dedicated silicon foundries, is forging a customized approach to outsourced semiconductor manufacturing by building lasting and collaborative partnerships with its customers. GLOBALFOUNDRIES' focus on enabling system-level technologies facilitates the convergence of communications, computing and consumer electronics. We operate with our customers' overall objectives in mind by providing complete solutions enabling them to deliver better, faster and cheaper products to market. Technology expertise is key to success in our industry. At GLOBALFOUNDRIES we are helping to accelerate the technology convergence taking place in the electronics industry, by anticipating the changing needs for our customers. Whether our customers are integrated device manufacturers, fabless, or system companies, they need the fundamental building blocks in silicon to address the cost-effective system solutions that today's and tomorrow's convergence applications require. The design of today's complex integrated circuits requires state-of-the-art electronic design automation (EDA) software tools, design intellectual property (IP), and design services. GLOBALFOUNDRIES supports customers in achieving successful designs by partnering with leading providers in the EDA, IP, and design services areas. This enables our customers to integrate system-level functionality in their products with accelerated time to market along with reduced design and manufacturing risks. We work with our partners very closely on technical and business aspects, providing our customers an advantage of having the best technical solutions available in a seamless fashion. GLOBALFOUNDRIES has an active alliance program to validate our partners' EDA tools, libraries and design IP with our silicon process technologies to insure that they meet the highest standards. FEATURES: DDR I/O (DDRI/II) General Purpose I/O (Inline / Staggered) Register File Memory Compilers Specialty I/O (HSTL, SSTL) SRAM Memory Compilers Standard Cell Libraries [...] (+)

      Features:

  • GOEPEL electronic  (1)
    • SYSTEM CASCON
      SYSTEM CASCON comprises the CASCON GALAXY and CASCON POLARIS software suites and works with the award-winning Boundary Scan hardware platform SCANFLEX (+)

      Features:

      34436.jpg
      • Tight integration of all software tools within one software application streamlines the test development process
      • JTAG/Boundary Scan software suite for test and in-system programming for FLASH, PLD/FPGA and serial EEPROM at board level and in system environments (such as AdvancedTCA)
      • Fully IEEE 1149.x compliant (JTAG/Boundary Scan per IEEE 1149.1, 1149.4, 1149.6
  • Highland Technology, Inc.  (1)
    • V370/375 ARB
      64 to 65,536 discrete points per waveform at up to 15 MHz (+)

      Features:

      • Independent or synchronized channel operation
      • 32-bit frequency and 16-bit amplitude resolution
      • Four TTL-level sync pulses, two TTL-level aux logic inputs
  • I-Logix, Inc.  (1)
    • I-Logix Rhapsody
      Rhapsody is the industry's leading Model-Driven Development (MDD) environment for systems, software, and test. (+)

      Features:

      • A seamless environment for Systems and Software Development with complete design portability
      • Flexible design environments supporting SysML, UML 2.0, DoDAF, and Domain Specific Languages
      • Integrated Requirements modeling, traceability and analysis
  • Impulse Accelerated Technologies  (2)
    • Impulse CoDeveloper, Impulse C
      Enter device independent FPGA designs using ANSI C and compile into Altera or Xilinx (+)

      Features:

      • Work within Visual Studio, GCC, Eclipse, or other standard IDEs
      • Cab mix with VHDL code if desired
      • Identify hotspots for acceleration
    • Impulse CoDeveloper
      High-level FPGA design software (+)

      Features:

      • Allows C-language algorithms and applications to be compiled and optimized for use with FPGAs
      • By using Impulse C and the Impulse CoDeveloper C-to-FPGA tools, users have the power to accelerate C algorithms by orders of magnitude (as much as 300X) over equivalent embedded processor implementations
      • Enter designs in ANSI C
  • Macraigor Systems, LLC  (1)
    • USB 2.0 JTAG
      Available for ARM, Xscale and PowerPC processors. The usb2Demon and usb2Sprite devices are identical in functionality, but differ in speed to provide embedded developers with flexibility in choosing an appropriate price/performance ratio for their projects. (+)

      Features:

      • Both new devices support Windows and Linux hosts and are fully compatible with all of Macraigor's software tools, including the Flash Programmer, J-Scan suite of JTAG hardware debug tools and the free, low-level OCD Commander debugger and pre-built GNU tools suite.
      • Macraigor's OCDemon family of products offers the industry's most advanced yet price-sensitive solution for designing, debugging and programming embedded hardware and application software.
      • Debug application programs are available to support an embedded project through the entire development cycle, from troubleshooting a prototype hardware design to writing and debugging boot code, programming in-circuit Flash devices, developing application-level software, and supporting manufacturing burn-in and testing.
  • Sequence Design  (1)
    • PowerTheater-Explorer
      new analysis environment lets large design groups employ PowerTheater engines for power estimation and multiple PowerTheater-Explorer visualization and debugging tools (+)

      Features:

      33438.jpg
      • “Users will experience immediate productivity gains when using PowerTheater-Explorer,” said Sequence president and CEO Vic Kulkarni. “It provides access to more power data that can be manipulated at both the RTL and gate levels of abstraction than any other solution.”
      • The hierarchical RTL power tree display shows hot spots that can be cross-probed to schematics, indicating how activity is moving through the design and how instances affect one another. The integrated waveform viewer in PowerTheater-Explorer can input qualified vectors for all modes of operation and report average modal power for package selection or worst-case for preventing dynamic voltage drop problems. Waveforms can be viewed simultaneously to debug power problems, including power over time, peak power, and comparisons between logic and power waveforms [...]
  • Startech Global  (1)
    • ATCA R&D Services
      Startech Global specializes in offering product engineering services and systems solutions for AdvancedTCA, MicroTCA, and AdvancedMC design anddevelopment (+)

      Features:

      32836.jpg
      • Board Design: Architecture, PCB design, power optimization, shelf management, high-level hardware synthesis
      • Prototype Development: PCB prototyping and testing, ATE, NDT, in-circuit testing/BIST, boundary scanning
      • FPGA Design: EDA; Xilinx, Altera chips; programming, pin assignment, board design & implementation, ATE
  • SynaptiCAD, Inc.  (7)
    • VeriLogger Extreme
      VeriLogger Extreme is a high-performance compiled-code Verilog 2001 simulator that offers fast simulation of both RTL and gate-level simulations with SDF timing information (+)

      Features:

      34718.jpg
      • Comes with BugHunter Pro a graphical Verilog/VHDL integrated development environment
      • Supports source-level debugging, with breakpoints that are saved a the project level and are not lost after code changes
      • Waveform compression engine for high-speed waveform dumping
    • Gates-on-the-Fly
      Gates-on-the-Fly (GOF) graphically analyzes and edits large Verilog netlists that have been generated from a synthesis or layout tool (+)

      Features:

      43569.jpg
      • GOF can edit Netlists that require changes to either meet timing closure specifications, fix functional logic bugs, or to repartition a design
      • Using GOF, you can easily find and view specific logic cones in your design on a schematic to visualize just the paths you need to see without unnecessary clutter
      • GOF also simplifies mapping from RTL level constructs to their gate-level equivalents, so that you can pinpoint the locations where changes need to be made
    • Verilogger Extreme
      VeriLogger Extreme is a completely new, high-performance compiled-code Verilog 2001 simulator that significantly reduces simulation debug time (+)

      Features:

      43729.jpg
      • VeriLogger Extreme offers fast simulation of both RTL and gate-level simulations with SDF timing information
      • VeriLogger Extreme supports design libraries and design flows for all major ASIC and FPGA vendors, including Actel, Altera, Atmel, LSI Logic, QuickLogic, and Xilinx
      • BugHunter Pro graphical debugger included with purchase of VeriLogger Extreme [...]
    • BugHunter Pro
      BugHunter Pro is a debugging environment for VHDL and Verilog simulators that provides unit-level test bench generation, exceptional VCD support, and project management (+)

      Features:

      • The unit-level test bench generation is unique in that it lets the user draw stimulus waveforms and then generates the stimulus model and wrapper code and launches the code
      • It is one of the fastest ways to test a model and make sure that everything is working correctly
      • Waveform window displays both the simulation results and the stimulus waveforms for the test bench generation
    • WaveFormer Pro
      WaveFormer Pro combines a timing diagram editor, a stimulus generator, and an interactive HDL simulator (+)

      Features:

      • Automatically generate and simulate timing diagrams using common Boolean and registered logic equations
      • Import or export waveforms to VHDL, Verilog, HP's logic analyzers and pattern generators, SPICE, ABEL, and a variety of gate-level simulators
      • Download WaveFormer Pro from www.syncad.com [...]
    • VeriLogger Pro
      Verilog simulator with built-in unit level testing features for FPGA debugging (+)

      Features:

      • Waveform viewer
      • Debugging environment
      • Color-syntax editors
    • Transaction Tracker
      Transaction Tracker is a PSL/Sugar-based verification tool for viewing simulation data as higher-level transactions, instead of as simple waveforms (+)

      Features:

      38879.jpg
      • Transaction Tracker can read VHDL and Verilog simulation results, Agilent and Tektronix file formats, plus BTIM files (SynaptiCAD's 200x-compressed binary format)
      • SynaptiCAD's gigawave feature is included with Transaction Tracker stand-alone, allowing gigabyte-size files to be loaded into the tool
      • Equations are written in the PSL/Sugar language
  • Synplicity  (2)
    • Synplify Pro
      Achieves industry-leading QoR by incorporating several advanced optimization techniques including proprietary Behavior Extracting Synthesis Technology (+)

      Features:

      31751.jpg
      • By extracting behavior such as Finite State Machines, multipliers, and memories from RTL code and starting synthesis at this level, the Synplify Pro product optimizes a design globally for improved performance and at the same time can run faster and handle larger designs
      • By selecting a switch, a designer can tell the tool to automatically move registers inside combinatorial logic in order to balance timing delay and improve circuit performance by as much as 20 percent
      • Retiming may be used on a global level or selectively
    • Synplify DSP
      Model and simulate algorithms quickly, and automatically create optimized RTL implementations for a wide range of target devices (+)

      Features:

      31747.jpg
      • Automated RTL implementation
      • Automatically generates RTL and a verification test bench from a Simulink system-level specification
      • No hand-coding of any RTL is required
  • Tarek Verification Systems  (1)
    • PCIE-VR
      Supports all the PCI Express standards, 1.0a, 1.1, and the coming Gen2 (+)

      Features:

      • All PCIE designs, such as root complex, switches, end points, and bridges, are supported at both Register-Transfer Level (RTL) and Electronic System Level (ESL)
      • To integrate a PCIE design, PCIE-VR uses standard interfaces, such as serial, PIPE, 8/10b, and parallel
      • A compliance test suite that implements the PCIE compliance checklist from PCI-SIG is also included
  • Target Compiler Technologies  (1)
    • IP Designer
      Finding the right balance between efficiency and flexibility requires the ability to quickly evaluate alternative architectures. IP Designerâ„¢ offers a complete retargetable tool-suite for exactly this purpose. With IP Designer, designers can define their ASIP architecture in the nML language. Automatically the IP Designer tools will work for this newly specified ASIP. nML is the first commercially available high-level definition language, that quickly evolved to become the de-facto standard to describe a processor architecture and instruction set (ISA). nML offers designers the abstraction level of a programmer's manual of a processor. FEATURES: Chess is a software compiler that maps C application programs into highly optimised machine code for the target ASIP. Chess can cope well with architectural peculiarities of DSP cores. Chess supports instruction-level and data-level parallelism, deeply pipelined instructions, specialised arithmetic functions, custom data-types, specialised address generation units, heterogeneous register structures, and various degrees of instruction encoding (ranging from VLIW to highly encoded instruction sets). Chess produces machine code in the Elf/Dwarf object file format. Bridge is a linker that builds an executable file from separately compiled Elf/Dwarf object files for different C functions. Darts is an assembler and disassembler that translates machine code from assembly into binary format and back. Checkers is an instruction-set simulator (ISS) and graphical debugger generator. The ISS offers bit-accurate execution of machine code, both at cycle-accurate and instruction-accurate level. Through a co-simulation interface, the ISS can easily be coupled to other simulators (e.g. co-simulation with an RTL model or with other ISSs, or integration in a SystemC or virtual platform model). Checkers supports C source-level debugging based on Elf/Dwarf executable files. Checkers' graphical debugger can also connect to the processor hardware to support on-chip debugging. Checkers produces execution profiles to drive the optimisation of the ASIP architecture and of the application software. Go is an RTL generator that translates the nML processor description into synthesisable register transfer language (RTL) hardware modell. A JTAG interface and a debug controller can optionally be generated, to support on-chip debugging. Risk is a test program generator that generates processor-specific assembly test programs. ChessDE is a graphical integrated development environment that integrates all the above tools. [...] (+)

      Features:

  • Tuscany Design Automation  (1)
    • Tego
      Physical Design Software to Accelerate Structured Design (+)

      Features:

      • Deterministic design closure
      • With performance, power and area as primary objectives, another key value is that structured physical designs generally follow a systematic and predictable path to closure
      • Closure usually comes faster than by traditional techniques involving more trial-and-error
  • VaST Systems Technology  (1)
    • Virtual Prototype
      VaST virtual system prototypes consist of fast, accurate, software tools and models for system-level engineering of SoCs and real-time and embedded systems (+)

      Features:

      • Consists of VaST models of multiple processors, complex buses, and peripheral devices
      • VaST models run at speeds or 20-200 MIPS; timing accurate with cycle-by-cycle bus arbitration
      • CoMET is the VaST tool used by architects and systems designers for architecture exploration and optimization
  • XILINX, Inc.  (3)
    • Virtex-6 FPGA DSP Kit
      Provides a platform for next generation products that include digital signal processing (DSP) which need to deliver more performance and flexibility with shorter development cycles and less cost and power (+)

      Features:

      44697.jpg
      • Out-of-the-box development solution that quickly builds confidence in developing DSP applications on FPGAs
      • Includes a Xilinx ML605 development board including a Virtex-6 LX240T FPGA, design tools, IP, reference designs, and documentation
      • Supports both traditional RTL and high-level design methodologies and can easily extended to include additional high-level design flows and I/O daughter cards through third party partners and standardized integration [...]
    • Zynq UltraScale+ MPSoC
      Based on the Xilinx UltraScale MPSoC architecture, the Zynq UltraScale+ MPSoCs enable extensive system level differentiation, integration, and flexibility through hardware, software, and I/O programmability. (+)

      Features:

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      • Innovative ARM® + FPGA architecture for differentiation, analytics & control
      • Extensive OS, middleware, stacks, accelerators, and IP ecosystem
      • Multiple levels of hardware and software security
    • Xilinx ISE Design Suite 11
      ISE Design Suite 11 Embedded Edition delivers base-level FPGA features and technologies, plus all the embedded tools and IP needed to achieve greater design productivity and breakthrough performance, power, and cost benefits with Xilinx embedded processing solutions (+)

      Features:

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      • Platform Studio Design Suite and the EDK: Integrated development environment with embedded processing tools and design generators, MicroBlaze soft core, IP, software libraries, and third-party interfaces
      • Software Developers Kit (SDK) as stand-alone configuration: Eclipse-based software development environment for feature-rich C/C++ code editing and compilation, source code version control, and seamless debug and profiling of embedded targets
      • System Generator integration with SDK: Enables algorithm developers to use only the software development environment for the embedded portion of their designs [...]
10/1/20 14:03
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