DSP

New entrants target the need for custom DSPs in wireless applications

May 22, 2012 — Mike Demler, Editorial Director

The demand for various forms of connectivity continues to explode, driving more complex requirements for flexible, high-performance, yet low-power DSP in multi-mode baseband processors. In designing a DSP for wireless applications, engineers are challenged to support an increasing number of air interfaces and protocols, from multiple 3G and 4G configurations to new modes of with IEEE 802.11ac, Bluetooth 4.0, Near Field Communication (), Digital TV (DTV), and wireless display technologies.

As more semiconductor vendors are drawn to this growing market, designers face the often difficult task of choosing from among several competing silicon options in which to implement their design. If Application Specific Standard Products (ASSPs) or can’t meet all the requirements for performance, power, and functionality, customizing a DSP SoC may be the only solution.

Creating efficient custom multi-mode SoCs

Providers of Silicon Intellectual Property (SIP) for DSPs offer varied architectures from which to construct custom multi-mode SoCs. One approach is to use Software Defined Radio (SDR) techniques, which DSP IP provider CEVA proposes is an optimal solution when implemented with their universal modem engine. CEVA emphasizes the fine-grained power management features of their architecture, which is critical to maximizing battery life in portable applications. Hardware-software partitioning also has an impact on power efficiency, so CEVA employs Tightly Coupled Extensions (TCEs), hardware accelerators that offload their processors for common functions. The TCEs can also be user-defined. For a complete DSP, designers will typically assemble multiple heterogeneous CEVA-XC cores according to the application, with software provided by CEVA and their partners.

Tensilica also provides SIP for designers of custom DSPs, centered around their ConnX DSP engines. Speaking at the Linley Tech Mobile Conference on April 16, Tensilica CTO Chris Rowen said their architecture also targets power efficiency by combining dedicated task engines for functions such as Fast Fourier Transforms (FFTs) in a heterogeneous arrangement with the ConnX DSP core and other Tensilica Dataplane Processor Units (DPUs). Tensilica supports a C programming model for the ConnX engine, providing for automatic mapping of C functions to ConnX advanced DSP operations. Designers can customize their architecture or modify I/O interfaces, the parameters of the computational units, and the memory subsystem with Tensilica tools by adding their own instructions.

Connectivity options

ASOCS CEO Gilad Garon addressed the issue of air interface complexity at the Linley Conference, proposing that new communications architectures, which he called “3D,” are called for in order to seamlessly move from network to network. ASOCS is an Israel-based provider of licensable DSP IP, offering their ModemX architecture. Garon said that ModemX is different than other SDRs because the processor can change communication protocol dynamically. In ASOCS’s proposed architecture, a software-programmable core must be capable of concurrently operating a variety of radio interfaces, from Wi-Fi to Bluetooth to 3G or 4G, and switching a user’s communication link to the optimal protocol at runtime.

The architecture of a ModemX DSP is an array of dedicated processors, which ASOCS refers to as Algorithm Processing Units (APUs). (Not to be confused with AMD’s Accelerated Processing Units). All APUs are contained with the same wrapper for control and timing and interfacing to the rest of the system. Essentially, a DSP built with the ASOCS methodology results in a fine-grained multiprocessor architecture, which enables fine-grained management of supplies and clocking for power savings. ASOCS’ ModemX architecture makes use of a large number of heterogeneous cores, as many as 800 to 1,200 says Garon, for some cellular base station applications. ASOCS typically uses multiple instances of 16 to 20 different cores, each representing the hardware implementation of a specific algorithm. Designers must select the protocols and determine the worst-case concurrency scenario for their design before fabrication in silicon. Garon acknowledged that the tradeoff with ModemX is more complex software, which requires a combination of C- and assembly-level programming. In his opinion, such low-level programming will be mandatory in the future to support the level of concurrency that ASOCS designed into their architecture.

A complete package

A new DSP design company, Algotochip, came out of stealth mode at the GlobalPress Electronics Summit on April 23. Algotochip combines aspects of a SIP provider and a design services company, with the objective of helping customers achieve the long-held ideal of a direct path to DSP silicon from C-language algorithmic descriptions. Algotochip’s CEO says that the Electronic System Level (ESL) design ideal of synthesis directly from a high-level description never came to reality because it is not possible to completely model a cycle-based system using just C or System-C. Inputs to the Algotochip methodology are any sequential C-language description of the DSP algorithm, a set of test vectors for the code, and a textual description of the system specification, along with a selection of the target manufacturing process. Algotochip does the hardware-software partitioning based on their knowledge of the system specification and their experience as DSP developers. Customers do not need to learn how to use any of Algotochips’ proprietary tools since the company considers themselves an R&D partner and not a tool provider.

Algotochip uses standard tools from Design Systems, Mentor Graphics, and for synthesis, logic simulation, and physical implementation, and does power analysis with Apache tools to create the architecture. Output is produced in and GDSII form and customized and optimized for manufacturing processes at TSMC and UMC foundries. They also supply a Software Development Kit (SDK), which includes an assembler, linker, compiler, cycle-accurate simulator, and the firmware for the custom DSP. The company currently supports implementation in an ASIC flow, and is working on providing the same capability for FPGAs.

The Algotochip process results in a custom programmable solution, including a microcontroller and DSP with customized hardware accelerators that are specific to the customer’s application. The Algotochip design is license-free, so customers don’t need to pay any separate fees or royalties. The open standard ARM SoC interconnect bus is supported for connection to peripherals and does not require licensing fees either, so everything is owned by the customer when the project is completed. The company says they can typically produce a design within 8 to 16 weeks, and will also create an prototype for functional verification.

The future of custom DSPs

Designing a custom DSP can be a challenging and expensive undertaking. However, the ecosystem of SIP, EDA, design services, and software providers are addressing the problem with solutions that can ease the process with higher levels of automation and more efficient methodologies. The custom DSP segment will be a growing battleground, with more competition between FPGAs and ASICs to provide both the flexibility and fine-tuned architectures that are best-suited for multi-mode wireless applications.

The need will only increase, as FCC Chairman Julius Genachowski remarked in his keynote address at the CTIA Wireless show on May 8, “the demand for mobile services is on pace to exceed the capacity of our mobile networks.” For mobile networks, solutions include smarter antennas and smaller cells, but the FCC also plans to accelerate re-farming of unused spectrum from older technologies to . More frequency bands will come online, driving demand for smarter DSPs and more multi-mode baseband processors. More integration with Wi-Fi is also a requirement, as the FCC is looking to open up another 120 MHz of spectrum in the 5 GHz band for unlicensed use. The good news is that, as the airwaves continue to get more crowded, more opportunities will be created for designers of custom, efficient DSPs.

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