CEVA is a developer of Digital Signal Processing (DSP) cores, which they license in the form of synthesizable (i.e. soft) Intellectual Property (IP) for integration in Systems on a Chip (SoCs). By partnering with providers of application-specific software IP, CEVA has been able to adapt the soft-modem architecture of the CEVA-XC323 core for use in a variety of applications, such as Global Positioning Systems (GPS) and 3G/4G wireless infrastructure equipment. Mindspeed has licensed the CEVA-XC323 as the core of their software-defined radio in the Transcede processor for LTE base stations. Now, in preparation for the upcoming January 2012 Consumer Electronics Show (CES), CEVA has announced a collaboration with IDEA! Electronic Systems to apply the CEVA-XC323 in Digital Television (DTV) demodulators, starting with the Integrated Services Digital Broadcasting Terrestrial (ISDB-T) standard which is used in Japan, Brazil and other countries in South America.

Eyal Bergman, Director of Product Marketing at CEVA, says that TV manufacturers have a need for a single, universal demodulator chip that can support the variety of standards that have been developed for terrestrial, satellite, cable and mobile TV broadcasting. Currently, manufacturers need to maintain inventories of multiple standard-specific DTV demodulators, says Bergman, in order to address markets worldwide. A universal software-defined DTV demodulator will eliminate that problem, and enable integration of the function into application processors in 2-3 years, according to Bergman.

CEVA’s Bergman says that the lack of a universal DTV design has been a barrier to SoC integration up until now, but that he expects that application processor vendors such as Qualcomm and Texas Instruments are working to incorporate such functions in the future, targeting tablet computers that are expected to increasingly be used as alternate screens for viewing TV content. He contrasts the CEVA approach, based on a communications-specific DSP core, to competitors such as Mirics who build their software demodulator on general-purpose processors such as ARM cores. These solutions have relatively weak processing capabilities, says Bergman, and result in higher cost for embedded applications.

In comparison, CEVA’s approach is to build a complete software-defined subsystem by combining the XC323 core with the appropriate hardware accelerators and interconnect fabric required for a targeted application. In this latest example, by partnering with IDEA! for the ISDB-T IP, CEVA has been able to develop a software-defined DTV reference platform. SoC integrators can make use of CEVA tools and software libraries to configure a device for multiple DTV standards. Original Equipment Manufacturers (OEMs) can then modify and control the platform in specific TVs through software APIs. At CES, CEVA and IDEA! will demonstrate the DTV reference platform on an FPGA-based prototype of a complete ISDB-T receiver.

As FPGAs become more popular in the electronic design community, the approaches and tools used to integrate analog functions such as ADCs with these digital chips must be refined. Customer demand for high reliability, small footprint, and low power means that engineers have few choices and must look outside the box in their approach to mixed-signal integration with FPGAs.

FPGAs have exploded in popularity in recent years due to their relative low cost and high performance for digital signal processing tasks. The advantages of digital processing, reprogrammability, and variable cost structure have fueled this fast growth. Ironically, as the world has gone “digital,” demand for analog chips and components to grab continuous, real-world data has also risen quickly. As the breakeven unit decision between FPGA and ASIC continues to narrow, one large challenge continues to exist: For the FPGA market to continue growing, digital engineers need robust tools and effective solutions to integrate mixed-signal functions in their digital designs.

Three approaches generally exist for integrating Analog to Digital Converters (ADCs) with FPGAs: external off-the-shelf components, “mixed-signal” FPGAs, and digital ADC implementation. The traditional approach is to add off-the-shelf external ADC components. FPGA manufacturers responded to market demand for analog functionality by introducing “mixed-signal” FPGAs with ADCs in the packaged device. These mixed-signal FPGAs have significant advantages and a few drawbacks (really, when do we engineers ever get exactly what we want?). A third approach, which can fill in the gaps for many applications, is to use a digital ADC IP core to implement ADC functionality directly in the digital fabric of an FPGA. All three approaches are significantly different and require different flows and tools for effective integration.

The external components approach

The traditional integration of ADCs with FPGAs requires external parts. The process involves sourcing and selecting the proper component from an analog parts vendor and understanding how that component will affect size and power budgets. Tradeoffs exist between size, power, and performance. For many applications where size and power are not an issue, this approach works very well. Mixing and matching parts can be an easy way to meet cost budgets for projects that do not require strict optimization. Additionally, for very-low-volume applications, this may be the best approach as many simple ADCs are low cost. However, with the drive to low-power, portable, and high-reliability electronics in consumer, military, medical, and aerospace applications, there is room for improvement. In these markets any external connection point is a possible point of failure, so decreasing external part count would be very valuable. Lastly, for these same markets, system certification or recertification is an issue due to possible discontinuation of a part by a vendor. Certification requires significant resources to be achieved, and is easiest if done only once. In space exploration, this can be of particular concern.

Tools for external part verification

Verification at the PCB level can be divided into two arenas: small designs below 50 MHz operation and complex designs above 50 MHz. Smaller designs below 50 MHz can be verified using interface timing diagrams and a scope. The higher-speed designs require simulation tools such as HyperLynx[1] from Mentor Graphics, which is capable of board-level verification, signal integrity, and other features. Like all simulators, board-level simulators also require good models. Most ADC part vendors provide models with their semiconductor devices. However, when an FPGA design is involved it takes additional time and resources to generate the cycle equivalent model(s) for the FPGA to support PCB simulation. No matter the size, speed, or complexity of the PCB design, using a CAD tool like HyperLynx will verify and validate signal integrity and ensure faster design times.

The “mixed-signal” approach

FPGA vendors have done a good job of responding to the market’s need for ADC inte-gration. Xilinx and Microsemi have great approaches to covering the broad market. By placing one or two 500 KSps or 1 MSps ADCs in the package most applications are covered. These packages are more reliable than the external components approach, and have a smaller overall footprint. These mixed-signal FPGAs naturally command a price premium over other FPGA families for providing packaged ADC functionality. Depending on the product strategy and cost structure, the price premium may be well worth paying. For instance, if the product strategy is to constantly lead in terms of performance, it probably also commands a price premium, and the unit costs may not be that big of a deal. On the flip side, if it has a “continuous cost cutting” strategy, living with this approach may be required until needs can be met more adequately.

Customization is not much of an option in this approach. ADC resolution, sample speed, and number of channels are generally fixed by the vendor. This allows FPGA vendors to support a large swath of the market, but may come at the expense of the power budget. For example, running a voltage measurement at 1 MSps is like using a sledgehammer to drive the head of a pin. The extra speed will negatively impact the power budget. Complex designs these days can require upwards of 48 measurement channels. With mixed-signal FPGAs, adding external analog multiplexers or more mixed-signal FPGAs is the only solution to accommodate the number of channels.

Mixed-signal FPGA simulation and verification tools

Currently, FPGA tools for true mixed-signal simulations are not available. ModelSim[2], however, does support mixed languages such as Verilog, VHDL, and Verilog-A. Depending on the complexity of the analog portion of the design, ModelSim can be used to validate functionality at the mixed-RTL level. A mixed-signal simulator should be used to determine analog performance. However, to determine actual performance a true mixed-signal simulator should be used, such as Mentor ADMS[3] or Cadence AMS[4]. They will also require accurate SPICE models to determine performance, which might be difficult to obtain. Both methods take simulation time or functionality, and more simulation time to determine actual performance.

Digital implementation approach

Some “analog” functions can also be im-plemented using only the digital fabric of an FPGA or ASIC. A crude scheme can be worked up by using an LVDS and small set of resistors and capacitors (Figure 1). Several white papers from Xilinx, Lattice, and others exist on the topic. These papers show resolutions of only 8-9 bits while requiring very high clocks to achieve that performance. Additionally, error rates have been shown upwards of 15 percent.

External ADCs are unnecessary because a digital ADC is embedded in the FPGA fabric. The removal of external parts lowers board space, and the digital architecture and slower clocks lower power consumption over a comparable analog ADC. Testing is made easy by using the digital test methodology available from any FPGA vendor. These cores can be made rad hard/tolerant by using a rad-hard-tolerant FPGA.

Despite these many advantages, the generic digital ADC technique is severely limited in resolution and bandwidth. This approach will generally not work for applications requiring MHz bandwidths, such as RF communication, as those bandwidths are much more difficult to achieve with digital resources. Here, the external parts approach and perhaps the mixed-signal FPGA approach hold the advantage for those applications.

Through proprietary signal processing, Stellamar can achieve digital ADC performance upwards of 14-bit resolutions and 100 kHz bandwidth with error rates of less than 1 percent and no temperature drift. This method works for applications spanning DC measurements, temperature, touch, acceleration, motor control, audio, and some optical networking tasks. Stellamar works with Xilinx and Microsemi to provide Digital ADC IP cores to engineering teams that require a customized combination of low power, small size, and high reliability, and currently works with aerospace companies on satellite builds and with consumer electronics companies looking to reduce part count to lower cost and increase reliability.

Tools for digital simulation

Current FPGA tools are quite adequate to perform all digital simulation with an embedded digital ADC. This provides a level of certainty at the RTL and gate levels to the entire design before configuring an FPGA. This verification and validation is achieved by using any Verilog simulator supplied with the standard FPGA toolkit, which is ModelSim in most cases. Since a digital ADC is described in Verilog or VHDL, any FPGA can be targeted without the need for additional models other than the supplied FPGA digital library. With the added flexibility of reprogramming and the availability of different-sized FPGAs, designers can optimize not only the system by defining the exact ADC requirements, but also the power and board. A typical FPGA design flow starts with the instantiation of the digital ADC IP into the design. Then the entire design is synthesized to the FGPA gates using the tool provided with the FPGA toolkit. Post-place and route gate level timing simulation is usually performed with the provided ModelSim simulator to perform an all-digital simulation. This validates the gate level implementation of a mixed-signal design without the need of a mixed-signal simulator.

Reintegrating analog and digital

The growth of the FPGA market for high-reliability and low-power applications hinges on better integration of “analog” with “digital.” Three approaches for implementing ADCs with FPGAs are available. External components can be easy to use but occupy more board space. Mixed-signal FPGAs are easily accessible and offer great performance, but are technology-dependent, more expensive than standard FPGAs, and are limited in array size. Embedded Digital ADC cores are technology-independent and offer a migration path to ASICs, use digital testing, and are optimized for size and power; their main drawback is a limitation on bandwidth.

From a system perspective, the mixed-signal FPGAs and embedded Digital ADCs are best for systems that require certification, such as medical, consumer, and military devices, as they remove the possibility of a system change due to end-of-life of an external ADC.

Good mixed signal integration starts with understanding what signals are being measured and what is required to measure those signals. Once requirements are accurately established, an approach can be selected. No matter which method is used, a PCB simulation should be run at the board level in all cases. The ability to use a Digital ADC core can simplify the design integration and validation of an FPGA-based mixed-signal design.

Each approach and tool set have real value to the engineering team, but each have their drawbacks. Looking to the future, more analog functions such as power management and clocking will be able to take advantage of digital tool sets for modeling and testing.

References

1. Mentor Graphics HyperLynx: http://www.mentor.com/products/pcb-system-design/circuit-simulation/hyperlynx-signal-integrity/
2. ModelSim: http://model.com/
3. Mentor Graphics Mentor ADMS: http://www.mentor.com/products/ic_nanometer_design/events/adms_mixed_signal_workshop
4. Cadence AMS: http://www.cadence.com/products/pcb/ams_simulator/pages/default.aspx

Allan Chin is CEO at Stellamar and has more than 30 years of design experience with high-performance digital and mixed-signal systems. His broad expertise covers many areas of IC design, including system requirement definition, chip development, mixed-signal simulation, verification, prototyping, and lab testing. Allan has a B.S. in Electrical Engineering from Marquette University, Milwaukee, Wis., and holds nine patents. Allan can be reached at allan.chin@stellamar.com

Stellamar info@stellamar.com www.stellamar.com

]]> http://tech.opensystemsmedia.com/dsp/2011/12/approaches-and-tools-for-fpga-mixed-signal-integration/feed/ 0 http://www.dsp-fpga.com/articles/id/?5472 http://www.dsp-fpga.com/articles/id/?5472#comments Tue, 06 Dec 2011 15:00:00 +0000 Michael Parker, Altera Corporation http://tech.opensystemsmedia.com/dsp/?guid=af11d6a37963404e91e8a830d78fb1d2

Communications over the power grid presents several challenges including noise, attenuation, and distortion. Engineers must make the right trade-offs in defining and configuring power line communications systems to provide optimal performance.

Power Line Communications (PLC) enables intelligent Machine-to-Machine (M2M) communication in the evolving power grid to establish greater efficiency and productivity, streamlining energy delivery to the world’s increasingly integrated and demanding economy.

Given that the power grid is an established ubiquitous network, connectivity via PLC is potentially the most cost-effective, scalable interconnectivity approach for utility-side as well as consumer-side applications. Utility-side applications include automatic meter reading, dynamic rate management, load management, load profiling, and street light control/management systems. Consumer-side applications include smart appliance connectivity and home automation. Additional applications include other electrically connected devices requiring monitoring and control, such as vending machines, solar panels, electrical vehicle charging, and other data-gathering and control systems.

Narrowband PLC has been around for many years, but with recent advancements in technology, increasing needs in M2M connectivity, and awareness of better resource management, it is gaining momentum as the most ubiquitous network medium available.

Due to harsh noise and variations in equipment and standards, communications over the power grid is difficult. Engineers using PLC must optimize their designs to achieve the best combination of distance, data throughput, error rates (packet retries), and overall reliability. To meet PLC systems requirements, engineers must configure modulation, select modulation frequencies, determine the level of packet redundancy, and select appropriate signal levels.

Difficulties of communications over the power grid

The power line network presents a number of roadblocks for data transfer, as the primary design goal of the power line network is electric power distribution. It was not originally designed as a communication channel. Signals propagating along the power line are subjected to very large amounts of noise, attenuation, and distortion that make them erratic and frequently variable over time. As a result, data communications requires a modem whose configuration changes to match the variations that result over power lines.

Power line noise

Many noise sources on power lines result in interference, cross-chatter, and signal distortion. Electrical devices connected to the power mains can inject significant noise back onto the network. The characteristics of the noise from these devices vary widely and are classified as impulse noise or tonal noise. Impulse noise sources include light dimmers, motors, power line-based intercom modules, and impulses that result from power utility equipment switching. Tonal noise sources include switching power supplies (PCs and electronic fluorescent ballasts).

Signal attenuation

Attenuation results from the wiring topology of the power line infrastructure within buildings, between buildings and concentrators (low-voltage network), and connectivity to utility/substation equipment like transformers and switches (medium-voltage network). Attenuation levels vary greatly within a given location and across power line installations. It is not uncommon to observe attenuation variances from 2x to 500x (3 dB to 30 dB) in outlets of the same building and even in close proximity to each other. Note that adjacent outlets do not guarantee a short wiring path or less noise.

Attenuation is also caused by loss from transformer coupling, distribution wire cross-coupling, and multiphase load impedance. This results in attenuation in the range of 25 dB to 60 dB near 100 kH within the low-voltage network. PLC is also used across much larger distances (as far as 15 km on medium-voltage utility lines), leading to greater signal attenuation. Transformers and DC-DC converters attenuate the input frequency signal almost completely. Bypass devices become necessary for the signal to be passed to the receiving node.

So why not simply increase the transmit signal level to compensate for attenuation loss? While this is exactly what is done in a configurable PLC modem, signal amplitudes and total power on the channel are regulated. For Europe, the CENELEC standard limits signals to a maximum amplitude of 116 dBμV, with a frequency band from 9 kHz to 145.5 kHz divided into specific bands for electricity suppliers and consumers. In the United States, the FCC similarly limits signal and maximum power spectral density with a maximum frequency of 550 kHz.

Signal distortion resulting from power line impedance

Varying power line impedance distorts the communications signal. Varying impedance results from transformers, filters, and coupling devices connected to the power line and switched in and out at different times.

PLC design trade-offs

Table 1 shows the trade-offs PLC engineers make when implementing PLC designs.

To both enable data communications with the channel variations of PLC and make the appropriate trade-offs of communications distance, data throughput, reliability, and network cost requires real-time PLC modem configurability. What complicates the problem is the general nature of PLC experience – high variability, variable attenuation, noise, and phase distortion – that leaves only a few good channels available for reliable communications. Consequently, it is critical that the power line modem support multiple configurable data channels, as illustrated in Table 2.

Configuring PLC for maximum performance

Selectable modulation: Example trade-off of noise immunity and data throughput

Triple-carrier Binary Phase-Shift Keying (BPSK) enables 3x the data rate on a given channel when compared to single-carrier BPSK. For channels at frequencies with more noise, lower data rate and higher noise immunity BPSK modulation can be used at the expense of reduced data rate. For less noisy channel frequency, higher data throughput 3PSK is used. This allows trade-offs of data rate and performance in noisy environments.

Multiple individually configurable data channels: Example trade-off via number of channels and amplitude

As shown in Figure 1, selecting fewer data channels enables higher amplitude per channel to address attenuation issues. Additional channels allow more data through and possibly increase reliability due to data redundancy at the expense of lower signal-to-noise and increased error rate. Configuring each channel amplitude individually enables an amplitude boost of channels with the most attenuation while still meeting requirements that regulate maximum channel power. Real-time selection of the modulation frequency allows the PLC modem to avoid impulse noise that might prevent communications.

Example trade-off via data redundancy

Hardware data redundancy allows for reduced error rates resulting from noise. The same data packets can be transmitted over multiple channels, or different data packets can be used on each channel (see Figure 2).

Achieving reliable, high-throughput communications

Data communications over the power grid is difficult, mainly due to extreme variations caused by noise, attenuation, and signal distortion. To meet PLC system requirements, engineers must configure modulation, select modulation frequencies, determine the level of packet redundancy, and select appropriate signal levels. This challenging communications environment requires the PLC modem to be configurable in real time. With multiple configurable data channels, selectable modulation, data redundancy, configurable network protocol, and configurable automatic gain control, reliable, high-throughput narrowband communications over long distances is achievable.

Mike Holt is VP of marketing and sales at Semitech Semiconductor. He founded technology incubator and advisory firm Get2Volume in Singapore in 2006. Mike has 24 years of management experience in the high-tech industry, with 15 years at Silicon Systems and Texas Instruments in various leadership positions including product line manager for TI’s $200 million storage DSP division.

Semitech Semiconductor +65 6777 9750 info@semitechsemi.com www.facebook.com/pages/Semitech-Semiconductor/218770644802683?sk=wall @SemitechSemi www.semitechsemi.com

]]> http://tech.opensystemsmedia.com/dsp/2011/10/finding-the-right-combination-for-optimized-power-line-communications/feed/ 0 http://www.mil-embedded.com/articles/id/?5373 http://www.mil-embedded.com/articles/id/?5373#comments Fri, 16 Sep 2011 15:00:00 +0000 Amir Shafy, North Atlantic Industries http://tech.opensystemsmedia.com/dsp/?guid=8da04a2edc68fa84eb20d0d36afe3638

In modern military, aerospace, and industrial control systems, the Discrete I/O interface is so common that it is often overlooked in the early design integration phase. This can lead to missed operational envelope considerations and other interfacing issues that might yield further complexity, increased cost, and missed operational Size, Weight, and Power (SWaP) savings. Meanwhile, Discrete I/O interfaces have evolved from basic On/Off “workhorses” into more sophisticated, intelligent devices that meet the challenges of designing control systems with Discrete I/O applications. Input/output considerations and the benefits of these new Discrete I/O control systems are examined.

Discrete I/O, in its simplest definition, is the sensing or driving of two-state voltage/current sources. The two states (On/Off or High/Low) are commonly defined by the system power and GND buses for simplicity and robustness. Perhaps because it is the most common interface, it is frequently overlooked and considered relatively minor in the overall design of complex control systems; this oversight, however, can lead to last-minute design scrambles and unforeseen variables such as unusual rail voltages, unstable power supplies, and noisy actuators.

Many complex military systems, such as engine and power control, data distribution, navigation, positioning, motion control, and weapons and targeting have discrete interfaces dispersed throughout. Battery system interlocks, servo brakes, hatch closure mechanisms, and arming indicators are just a few examples of simple but effective areas for discrete interfaces. But today’s Discrete I/O is much more than a simple On/Off “workhorse”; it has evolved into a sophisticated, intelligent, programmable, and wide-operating envelope control device. Thus, a closer look at the input/output considerations and benefits of these more modern, COTS-based I/O control devices is presented.

Managing system design with programmable I/O

Discrete I/O, usually identified on a per-channel basis, is normally preset as an input- or output-type interface. As an input, the Discrete I/O is generally used to detect the state (On/Off) of a particular device. In a typical input configuration, Discrete I/O interfaces directly with common actuators, switches, push buttons, state sensors, relays, indicators, and many other similar control- or contact-type devices. As an output, the discrete is frequently used to control the state of a particular device. Configured as an output, I/O may directly drive relay coils, solenoids, incandescent lamps, LEDs, and many other devices. Cumulatively, discretes used as inputs are decisively managed to control outputs and vice versa. In fact, some complete control systems can be managed by Discrete I/O only. This flexibility allows last-minute additions or changes in the overall system to be maintained seamlessly.

Input considerations

Configured as an input, Discrete I/O interfaces are referred to as either voltage or contact sensing. In voltage sensing, the device source will drive the input to either the Low or High state. On the surface, this might seem like a very simple interface to manage. However, using multiple power supply rails for different sensor inputs can cause chaos for the system designer because different channels might require different threshold levels. Programmable thresholds on a per-channel basis enable the system engineer to address this issue much later in the design process. Knowing that the Discrete I/O can handle a wide range of voltage levels (typically up to 60 V) affords engineers more time for other design considerations. In contact-sensing applications – such as GND-OPEN or OPEN-VCC levels (see Figure 1 for detailed circuit implementation) – it is the “open” sense or “floating” voltage level (which is in an undetermined state) that usually requires more effort from the system designer to implement. In the past, an external pull-up or pull-down resistor would be added to provide the hard-level state change required. Today, fully programmable pull-up or pull-down current sources can be set to provide the level that transitions require.

Dealing with “relay chatter” poses another challenge. Relay chatter is the oscillation that occurs when mechanical contacts are initially closed and there is an inherent “voltage bounce” that could be interpreted as multiple-level changes. For example, if a dry contact switch is used to “arm” a sensor, multiple voltage transients over several milliseconds could cause multiple “re-arming” commands that might yield unwanted results such as a misfire. With the ability to program a selected time-span debounce filter for the discrete input, this issue is managed by effectively ignoring any spurious transients that might be interpreted as a real signal.

Programmable features such as input or output selection, adjustable current source with “pull-up” or “pull-down” capability, and variable programmable filtering save integration time because no external components (such as external sensor modifications, cabling additions, or added resistors) are required.

Output considerations

Configured as an output, Discrete I/O interfaces are often referred to as current sources (high-side drive), current sinks (low-side drive), or push-pull drives (sourcing or sinking, depending on state). For example, discretes can serve as the output drive for a multi-indicator flight status panel. The panel might have many different types of illumination devices including LEDs and incandescent bulbs. Each illuminating device might have its own requirements – some might be configured to turn on by applying a voltage and some by supplying the GND (or return). Incandescent bulbs also have inherent issues with initial current surge, whereby the filament, prior to heating up, might draw more current than the rated average steady state. For example, the wide-use legacy GE382 miniature indicator bulb is typically rated at 14 V/80 mA. The initial cold turn-on might actually yield a current draw 10x greater for 20 msec.

Since the discrete can handle initial current surges greater than the rated average current draw, the size of the component selections required for driving the indicator is reduced. This subsequently provides smaller size and overall higher channel density. Without specifically knowing which device is connected to which channel, the systems engineer would be required to research and customize the hardware design to interface with each device independently. The ability to program the type of output drive simplifies the engineering integration required. Additionally, a COTS-based Discrete I/O technology can drive any device “out-of-the-box,” saving time, effort, and engineering dollars. Push/Pull configurations (see Figure 2 for detailed circuit implementation) can also save space and weight in interconnecting cabling where two devices can effectively be controlled with one channel in a complementary On-Off-On configuration.

Incorporating fast response times

The simple discrete interface has evolved into providing more than just an On/Off interface and offers greater benefits. With the advent of DSP and FPGA technology, the once-basic Discrete I/O – originally limited to only slow sensing, slow driving applications – has emerged into new interfacing applications. For example, a simple parallel discrete transceiver can be realized and implemented for subsystem intercommunications, as individual channels are typically managed simultaneously in 16-channel “module banks.” Also, combined with a fast FET front end, integrating requirements such as an LED dimming control in addition to On/Off levels can be realized. Previously, performing dimming control with a discrete would involve additional circuitry to pulse the discrete output or VCC source, thereby complicating the integration effort.

Additionally, simple preconfigured routines can be implemented in the DSP and FPGA control circuitry so that pulsed outputs or inputs can be managed simply by programming a period and duty cycle. The update rate of discretes today is at 50 KHz as opposed to perhaps 100 Hz in the past, depending on the Discrete I/O design – quite an accomplishment realizing that voltage levels up to 60 V are switched. Having basic programmable control at the channel level may relieve system processors from maintaining a continuous pulsed train effort.

On-line background status and health monitoring with Built-In-Self-Test

Typically, embedded systems are located in strategic access areas and are difficult to maintain. In military systems where event failures cannot be tolerated, a Built-In-Self-Test (BIT or BIST) is paramount. The modern Discrete I/O design includes a background BIT for monitoring the health and status of each channel. The status can be polled or interrupted on specific events, such as “overcurrent detect.” Combined with the ability to read the actual voltage or current being sourced or the input from a sensor/load during actual operation (online, without shutting down the application), the operational status of all channels can be monitored without any redundant hardware or additional software overhead.

Supporting common platforms with high channel density

As the Discrete I/O is arguably the most common interface used in most embedded control platforms, there is often a need for many channels in a control system. For example, one (of many) flight control panels might have 40 indicators and 20 switches – 60 channels total. Another example might be a distributed control system interface used on modern amphibious assault ships. Controlling multiple subsystems such as engine control and monitoring, power distribution, weapons stores and status, navigation, and others yields literally thousands of Discrete I/O monitoring channels that must all be accessed, monitored, and controlled on a real-time basis. Networked subsystems via GbE (at the card level) can be interconnected, yielding a true distributed networked I/O system targeting individual areas.

With component size reductions, modern, state-of-the-art Discrete I/O interfaces can deliver the maximum channel density count versus programmability versus operational characteristics envelope (voltage and current). These designs typically employ a modular concept and – combined with common platforms such as VME, VPX, CompactPCI, and others – this concept can be combined to provide in excess of 130 channels per card. Combining the common card platform with processing capability (Figure 3), the Discrete I/O can be maximized for channel count and/or integrated with other I/O functions such as A/D, D/A, communications interfacing, and so on, for a complete distributed I/O package capable and programmable for any I/O application.

The evolution of the “workhorse”

The Discrete I/O, no longer the overlooked basic On/Off “workhorse,” has evolved into an intelligent, programmable, and wide-operating envelope control device. With continued dedicated engineering and close customer interfacing, common COTS products are available to simplify the system integrator’s daunting task. Companies such as North Atlantic Industries (NAI) have introduced COTS-based I/O interfacing products that meet wide operating-envelope demands, mitigating the costs of design and field risks commonly overlooked early in the control system design process.

Amir Shafy is a Product/Applications Engineering Manager for North Atlantic Industries (NAI). Amir has a Bachelor’s degree in Electrical Engineering and Technology (BSEET) and has held various engineering design and integration positions in the rugged MIL peripherals, embedded, and portable computing industries. He can be contacted at ashafy@naii.com.

North Atlantic Industries (NAI)

www.naii.com

]]> http://tech.opensystemsmedia.com/dsp/2011/09/all-discretes-are-not-created-equal/feed/ 0 http://www.mil-embedded.com/articles/id/?2252 http://www.mil-embedded.com/articles/id/?2252#comments Thu, 13 Sep 2007 15:00:00 +0000 Ron Huizen, BittWare http://tech.opensystemsmedia.com/dsp/?guid=6b96a547fe2e6cf78cdc74c4fbbe2b39

Real-time signal processing and the applications that utilize it are continually changing the electronics landscape. This market-driven phenomenon creates a demand for greater speed, effectiveness and portability, and the consumer wants it now. This dynamic continues to propel market growth and the pace of change is accelerating. For the semiconductor provider, that fast adoption means fast time-to-market along with a quick ramp-to-volume.

Real-time signal processing and the applications that utilize it are continually changing the electronics landscape. This market-driven phenomenon creates a demand for greater speed, effectiveness and portability, and the consumer wants it now. This dynamic continues to propel market growth and the pace of change is accelerating. For the semiconductor provider, that fast adoption means fast time-to-market along with a quick ramp-to-volume.

Signal processing is the link from the real world to the computing world. As increasingly complex algorithms are implemented using digital signal processing, the performance demands of these algorithms rise exponentially. For cost-sensitive, high-volume applications like cellular phones, set-top boxes, and PC graphics cards, this has driven the development of extremely specialized ASSPs. However, for many other applications, the only options for implementing high-performance digital signal processing have been general-purpose Digital Signal Processors (DSPs) and, more recently, Field Programmable Gate Arrays (FPGAs).

DSPs have typically been used to implement many of these applications. Although DSPs are programmable through software, the DSPs’ hardware architecture is not flexible. Therefore, DSPs are limited by fixed hardware architecture such as bus performance bottlenecks, a fixed number of Multiply Accumulate (MAC) blocks, fixed memory, fixed hardware accelerator blocks and fixed data widths. The DSPs’ fixed hardware architecture is not suitable for many applications that require customized DSP function implementations.

FPGAs provide a reconfigurable solution for implementing traditional DSP applications and offer higher DSP throughput and raw data processing power than DSPs. Since FPGAs are reconfigured in hardware, FPGAs offer complete hardware customization while implementing various DSP applications. Therefore, DSP systems implemented in FPGAs can have customized architecture, customized bus structure, customized memory, customized hardware accelerator blocks and a variable number of MAC blocks.

The functionality of today’s FPGA
FPGAs have included dedicated DSP capabilities since near the turn of the new millennium. Since 2000, the evolution of DSP performance offered with FPGAs has increased by 16 times to about 500 Giga Multiply-Accumulate operations per second (GMACS). In the same period, digital signal processors have increased in performance from 1.6 GMACS to today’s 8.0 GMACS. Many applications require only minimal DSP performance, equivalent to the performance provided by a low-cost FPGA (i.e. Altera®’s Cyclone® II devices, Lattice’s ECP2M family or QuickLogic’s Eclipse II family). However, for applications requiring the performance of many digital signal processors, a single high-performance FPGA (Altera’s Stratix® III or Xilinx’s Vertex 5 ) can replace those processors, thereby significantly reducing power, board space and cost as well as delivering more than equivalent DSP performance, as illustrated in Figure 1 and calculated in Table 1.

 Table 2. Calculations for performance evolution – FPGAs vs. DSPs

The performance argument
The key markets driving high-performance DSP requirements are wireless infrastructure; video broadcast equipment, medical imaging and military applications. FPGAs are the preferred programmable DSP platform that addresses these requirements.

FPGAs are being implemented in flexible channel element cards, as in third-generation basestation platforms that include an RF card and a channel card to support various standards and through vertical migration, various channel densities. The basestation can be configured with a minimum of channels or with a large build-out of channels utilizing the same fundamental architecture, while only changing the specific FPGA selection.

Third-generation wireless has largely gone wideband, pushing RF components beyond their linear range of operation. Leading-edge algorithms help address the challenges that require significant processing traditionally beyond the capabilities of DSPs. Mainstream wireless infrastructure equipment now relies mainly on FPGAs to provide the RF linearization processing as shown on the RF card in Figure 2. Of the major functionality on the RF card, all the digital processing shown in blue in Figure 2 can be integrated into a single FPGA. There are two main components in RF linearization: Digital Pre-Distortion (DPD) and Crest Factor Reduction (CFR).

Digital pre-distortion addresses the non-linear transfer function inherent in wide-band amplifiers by pre-distorting the signal to be amplified by an inverse function to that inherent in the power amplifier. This requires a feedback path from the amplifier into an adaptive algorithm that dynamically updates the inverse transfer function to compensate for variations in the amplifier equipment and changes that occur across operating temperature.

Crest factor reduction squelches peak signals to reduce the peak to average ratio of a signal going through a power amplifier. This enables a significant cost reduction in the power amplifier portion of a wireless basestation. Most wireless infrastructure manufacturers develop their own algorithms and thus utilize FPGAs for differentiation.

In addition to DPD and CRF, the RF card includes digital up conversion and digital down conversion. These functions are relatively simple filters, but require huge DSP bandwidth. It is the requirement to support these functions that have driven FPGAs to include many hundreds of multipliers on a single FPGA. The ability of an FPGA to support this huge processing bandwidth while integrating evolving DPD and CFR algorithms that has made FPGAs the defacto solution for the RF card digital processing of ASICs.

Another area where FPGAs are the preferred processing platform is in WiMAX baseband processing where the huge computational requirements of orthogonal frequency division multiplexing (OFDM) can only be met with ASICs or FPGAs based on Berkeley Design Technology, Inc. (BDTI), “FPGAs for DSP,” analysis report. FPGAs are being widely utilized for WiMAX basestation implementation as an alternative to ASICs. This is driven mainly by the early development nature of the WiMAX business with high mask costs and very high verification costs of complex ASIC development.

FPGAs that feature a large number of multipliers, huge on-chip memory bandwidth, massive I/O bandwidth, and the unique and complete flexibility of an FPGA architecture enabled by programmable logic deliver the same or improved DSP performance, with lower power while reducing system cost and decreasing board space.

System designers can create a board with one or several FPGAs that require dozens of DSPs and possibly multiple boards. Because FPGAs support vertical migration, the inheritant scalability of FPGAs, within the same package, a single board and system design can be easily scaled from low-end capabilities to the highest capabilities without requiring multiple board designs. This flexibility is a major advantage as it reduces product line engineering design and verification costs.

High-performance DSP capability in FPGAs
New levels of DSP functionality have been attained in recently announced FPGAs, with latest generation of Stratix series devices delivering up to 896 18×18 along with associated input and output registers and addition and accumulation logic. The implementation of DSP functionality in high-end FPGAs has been optimized in silicon to maximize performance with low silicon area and low power consumption. A silicon DSP block has two physical constraints: the amount of periphery and the amount of area used.

The DSP block periphery routes 144 input wires and 144 output wires as well as control signals. The area of this DSP block enables four 18×18 multipliers that align with the total number of input and output signals. At the silicon level, varying the ratio of periphery to area of a DSP block enables more I/O or more block-level logic. At the system level filtering and transforming algorithms rely on sum-of-multiplication operations for the majority of processing requirements. Optimizing the core area of a DSP block enables twice the number of sum-of-multiplication operations when required, thereby reducing the periphery I/O requirements relative to the overall computation. By completing more of a DSP algorithm within a DSP block, the overall silicon efficiency increases dramatically.

A DSP block with eight 18×18 multipliers and associated register, accumulator and rounding/saturation circuitry is shown in Figure 3. The use of the multipliers is limited by the output wires from the DSP block, not the area of the logic; this enables approximately 50% greater silicon efficiency.

The total DSP capability of the block peaks for standard algorithms using the sum-of-multiplication operations, such as Finite Impulse Response (FIR) filters or complex multiplies, and simultaneously reduces overall power and resource consumption by not requiring the use of the programmable logic fabric. The number of 18×18 multipliers increases dramatically when a sum-of-multiplication operation is included as part of the algorithm.

A major advantage of FPGAs for many system architectures is the availability of package vertical migration which enables a single board design to support flexible processing performance and cost without respinning the board. System architects use this capability to create products with various price points and performance capabilities without significantly affecting development costs or inventory.

Wireless infrastructure applications are an excellent example of how this flexibility is used. FPGAs used in flexible channel element cards support various standards and, through vertical migration, various channel densities. A basestation can be configured with a minimum of channels or with a large build-out of channels using the same fundamental architecture and only changing the specific FPGA selection. In many developing countries, the focus is on more flexible, upgradeable and service-rich equipment that demands this FPGA flexibility. In these far more price-sensitive regions, the same product can use a structured ASIC for very standardized functionality at reduced cost. A vendor employing this type of solution has a formidable technology advantage for increasing business flexibility without increasing engineering costs.

FPGAs provide much greater I/O bandwidth than competing DSPs for driving system processing requirements, while bandwidth is driven by data input/output and off-chip data storage.

FPGAs have evolved rapidly in the last few years as system-level development tools have enabled system architects to realize the flexibility, scalability, maintainability and high-performance signal processing and control architectures. These tools include DSP system modeling tools, system integration tools, control processing IP, automatic C-to-hardware accelerators and DSP-optimized application IP. Utilizing these tools, designers can rapidly build high-performance architectures that are exactly optimized to meet system requirements. Along with vertical migration and structured ASIC support, system architects can build-in scalability across product line requirements and implement many permutations of products to satisfy various market requirements, while realizing a substantial productivity gain.

The tools and IP necessary to develop architecture entirely within an FPGA are available today, but there are other reasons why a standard third-party processor might be required or desired within the system architecture. When used with an FPGA, a third-party processor can significantly increase system performance while reducing system costs, power and board space through an architecture technique called FPGA coprocessing. In FPGA coprocessing, the FPGA offloads processing-intensive algorithms from the third-party processor. Many systems use a control processor, a digital signal processor, and one or more FPGAs (in which the major processing load is executed), where the control and DSPs are used for legacy software, operating system requirements, or general suitability of processing toward the final application (such as Windows GUI control).

More and more, the core signal processing of high-performance systems has moved to FPGAs. FPGAs deliver the highest performance programmable DSP available in any semiconductor device. There is not a more-flexible system architecture solution available that spans performance, low power, low price, and product breadth and lifecycle requirements.

Paul Ekas is the Senior Product Manager in charge of the Stratix III and Stratix series product lines at Altera. Mr. Ekas has more than 20 years of business experience in electronic design automation and complex semiconductor systems. Prior to joining Altera, Mr. Ekas was a director of product marketing at Morphics Technology where he was responsible for the 3G WCDMA infrastructure product line. Mr. Ekas has also held sales and engineering positions at Mentor Graphics, Silicon Designs, and Seattle Silicon. He holds a BSEE and MSEE from the University of Washington.

101 Innovation Drive
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]]> http://tech.opensystemsmedia.com/dsp/2007/02/fpgas-rapidly-replacing-high-performance-dsp-capability/feed/ 0 http://www.vmecritical.com/articles/id/?1951 http://www.vmecritical.com/articles/id/?1951#comments Fri, 13 Oct 2006 15:00:00 +0000 Dave Barker, VMETRO, Inc. http://tech.opensystemsmedia.com/dsp/?guid=92a67593a7e1ea547416d3c81bd68c15

VME technology continues to evolve, and developers are looking at the VXS or VPX standards for many high-end, embedded, real-time DSP applications, especially in defense and aerospace. Each has strengths and weaknesses, but are VXS and VPX competing for the same applications or are they complementary technologies? How are these technologies being used today and how might they be used in the future? Here, we sort out fact from fiction.

With its leadership in Field Programmable Gate Arrays (FPGAs), Xilinx has been in the unique position to create a market segment within programmable logic: high-performance reconfigurable DSP. We’ll examine some milestones that brought the company to this new market segment, and provide a few predictions of what the future will bring.

Editor’s note: due to publishing lead-times, the author wrote this article before Xilinx’s recent announcement of its Virtex-5 family. Certainly, the author was aware of the V-5; however, that information was not in the public domain when the editors at dsp-fpga.com began working with David on this article. The Xilinx Virtex-5 press release is available here, and here are related partner releases. Editor Chris Ciufo was one of the select journalists to attend the exclusive Xilinx Media Summit in Palo Alto, CA on May 8th.

With its leadership in Field Programmable Gate Arrays (FPGAs), Xilinx has been in the unique position to create a market segment within programmable logic: high-performance reconfigurable DSP. Weíll examine some milestones that brought the company to this new market segment, and provide a few predictions of what the future will bring.

FPGAs as DSPs

The DSP market is one of the fastest growing semiconductor segments today. According to Forward Concepts, analysts expect this market segment to grow from $22 billion in 2005 to nearly $47 billion in 2010, representing a 16.5 percent Compound Annual Growth Rate (CAGR). Significant FPGA opportunities exist within this vast market, particularly in the high-performance DSP segment, classified as applications requiring greater than 1 billion Multiply Accumulates (MACs) per second.

Back to the future
Xilinx began its push into the high-performance DSP market in the late ‘90s with the introduction of the Virtex-II product family. As the industry’s first platform FPGA, the Virtex-II fabric enabled the immersion of hard IP such as multipliers, digital clock managers, and block RAMs. The next-generation Virtex-II PRO products took advantage of this technology by embedding the IBM PowerPC and multi-gigabit transceivers, which became a turning point for the high-speed serial, DSP, and embedded processor application space. With the Virtex-4 family, the concept of platform FPGAs was taken to the next level through the introduction of the ASMBL architecture, enabling multiple platforms within a family optimized for logic, DSP, and embedded processing application domains.

In late 2004, to further propel growth in the DSP domain, Xilinx established a dedicated DSP division. This division is chartered with actively developing and delivering programmable DSP system solutions to enable next-generation, high-performance products with faster time to market and lower development costs.

The new division introduced its DSP Roadmap in the fall of 2005 based on several strategic pillars including market focus, design methodology, tailored solutions, and the company’s partner ecosystem. Targeted specifically at the digital communications, wired/wireless, aerospace and defense, and Multimedia, Video, and Imaging (MVI) segments, the DSP Roadmap covers a broad range of products and services. Figure 1 illustrates the solution spectrum, which includes a broad range of Xilinx and third party solutions.

IP and solutions
Traditional IP offerings for DSP designers have been horizontal in nature and apply to many market segments. Elements such as FFTs, FIR filters/compilers, encryption, and linear algebra are good examples of horizontal building blocks. Xilinx also tailors its IP offerings to meet the needs of the vertical markets mentioned above. Figures 2, 3, and 4, respectively, show solution roadmaps for these market segments. Each contains specialized components or solution platforms designed specifically to serve the needs of the end market and represent the collective expertise of developers, application engineers, and field technical experts in conjunction with invaluable input from customers.

In addition to developing building block IP, Xilinx is moving toward sets of products that will specifically provide proof of concept, and in some cases, reference quality designs for adoption directly into customer solutions. Examples in the digital communications arena are in the 3GPP and W-CDMA standards in radio-shelf and baseband implementations. New areas of rapidly growing interest are the WiMAX standards and Pico cell architectures. Similar solutions are included in each of the other market-focused roadmaps.

Tools and methodologies
The Tools and Methodologies Roadmap shown in Figure 5 illustrates our desire to address the designer community in three major tiers: traditional Xilinx hardware, FPGA, designers, DSP development engineers, and system designers. Traditional hardware designers have used the Xilinx ISE software tools suite and will continue to do so.

DSP development engineers and systems designers will use tools such as the Xilinx System Generator for DSP (SysGen) tool and AccelDSP synthesis tool. SysGen in combination with The Mathworks’ Simulink product, provide a framework for doing model-based design – a methodology favored by system designers. AccelDSP creates fixed-point VHDL or Verilog modules from floating-point MATLAB code, thus satisfying a demand from DSP development engineers and DSP algorithm developers.

Third-party tools also exist in this space with tools from vendors such as Synplicity, Celoxica, The Mathworks, and others. This healthy tool ecosystem is necessary to satisfy the broad variety of design requirements today. A major thrust of tools development, by third-party developers and Xilinx, will be to increase the level of abstraction and reduce the level of hardware knowledge required to create FPGA-based DSP designs. The ultimate goal is to design without touching a line of VHDL.

Silicon
Xilinx Spartan and Virtex FPGA families have continued to evolve and include specific functions that optimize performance and power for specific application areas. XtremeDSP slices and embedded processors are examples of content directly aimed at the DSP field. The Virtex-4 generation includes subfamilies that allow focused concentrations of features for cost-optimized delivery.

The Xilinx Virtex-4 SX product family offers up to 512 XtremeDSP slices operating at 500 MHz, providing the ability to support complex wireless algorithms such as MIMO, beam steering, and those functions required in digital, front-end designs. It is a good example of a family aimed at high-end applications. Designers will increasingly use hard blocks such as the XtremeDSP slice in future advanced DSP architectures to reduce cost and power consumption while increasing performance.

A less developed segment is at the low and mid range, where families such as the Xilinx Spartan-3/3E devices bring low price points for high-performance DSP. The solution includes many features that enable designers to build highly efficient DSP systems, providing up to 22 GMACs per second for under $100. These devices are enabling designers to use FPGAs in customer premises equipment and in higher volume video applications such as plasma displays and automotive telematics applications.

Partner ecosystem
In addressing the partner ecosystem, Xilinx is acknowledging a successful strategy already employed throughout the industry. Collaboration with a broad set of DSP ecosystem leaders is a cornerstone of our DSP strategy and roadmap. Partners exist in five main areas: tools, IP, boards, services, and complementary devices.

What’s next?
To meet the market requirements for next-generation systems, and to further provide customers with a cost-effective alternative to increasingly expensive ASICs, Xilinx has invested heavily in the 65 nm process node. Advanced 65 nm technology is critical to meet customers’ needs for higher performance, increased capacity, lower power consumption, and lower system cost.

The next-generation 65 nm Virtex will follow the already established track of Virtex generations and will build on the success of Virtex-4, leveraging the ASMBL architecture to provide customers with even more optimized choices for embedded and DSP applications. Working in close partnership with hundreds of customers, Xilinx’s next generation will include further optimizations to address different segments of the high-performance DSP market. To protect our customers’ investments in intellectual property and expertise, it’s important to provide a natural migration path.

David Squires serves as director of DSP Division Marketing at Xilinx. In this role, David is responsible for the product marketing and customer-focused activities related to Xilinx DSP solutions. Before his current role, David served as director of the Advanced Products Division Product Planning Group, responsible for strategic product planning. He joined Xilinx in 1996. Before that, he held management positions at EPIC Design Technology and The CAD/CAM Group, both EDA startups. David’s career began at National Semiconductor where he served as linear design engineer and later as IC design manager. He received his bachelor’s degree in electrical engineering from McMaster University and a master’s degree from the California Institute of Technology.

For more information, visit the Xilinx website at www.xilinx.com.

]]> http://tech.opensystemsmedia.com/dsp/2006/08/the-xilinx-high-performance-dsp-roadmap/feed/ 0 http://www.vmecritical.com/articles/id/?1832 http://www.vmecritical.com/articles/id/?1832#comments Tue, 13 Jun 2006 15:00:00 +0000 Bob Walsh, TEK Microsystems http://tech.opensystemsmedia.com/dsp/?guid=3a5b986a19e2ed4669027248e28b7be0

VME is the preferred choice for many deployed systems such as those in high-rel military applications. And signal processing experts agree: FPGAs, with their inherent parallel processing architectures and high-speed off-chip serial interconnects, make ideal DSP engines. Coupled into mesh architectures and installed on VME boards using the VME Switched Serial VXS standard, FPGAs can rival standalone DSPs and dedicated cluster computers.

Medical imaging equipment manufacturers are under pressure from the healthcare industry to develop cost-effective, state-of-the-art diagnostic instruments based on advanced Digital Signal Processing (DSP) algorithms and bring these products to market quickly.

Medical imaging equipment manufacturers are under pressure from the healthcare industry to develop cost-effective, state-of-the-art diagnostic instruments based on advanced Digital Signal Processing (DSP) algorithms and bring these products to market quickly.

One such instrument that requires complex DSP algorithms is Computerized Axial Tomography (CAT scanner), which captures a series of cross-sectional views of body projections that can be intelligently assembled into three-dimensional images. Very large computational bandwidths are required when multiple projections are transformed into two- and three- dimensional views. The processing performance of the image-rendering system determines how quickly a physician gets the necessary data to diagnose and treat the patient.

The first stage of a CAT scanner is data acquisition where radiation level samples from multiple detectors are converted from analog to digital, digitally filtered, and collected for further processing. The second stage, called back projection, uses the inverse radon transform which is a multiplication intensive algorithmic processing method where samples representing each angular projection are assembled into a two- dimensional slice of the body. As the XRAY source moves around the body, different angular projections generate new samples and thus new slices, which are ultimately combined to form a three-dimensional image.

Traditionally, algorithms have been developed, coded and improved in software, primarily the C language, and implemented on a General Purpose Processor (GPP) CPU. When more performance was required, the C language was ported to a DSP processor such as an Application Specific Standard Part (ASSP) and optimized in assembly code. If still higher performance was required, the software implementation was transformed into a high-level hardware description language and implemented in an Application Specific Integrated Circuit (ASIC). Respectively, each processing option required more implementation time and complexity as it diverged from the initial algorithm optimization, particularly in an ASIC.

Today, a new spectrum of processing options using Field Programmable Gate Arrays (FPGAs) exists, providing higher performance than GPP and DSP ASSPs alone. Algorithm development is continually improved in software and then implemented with a mix of DSPs and/or (FPGAs). One effective option uses a PCI-based FPGA accelerator board that is added to a GPP computer. For more performance without resorting to ASIC implementations, the additional spectrum of FPGA solutions include:

• Using FPGAs to distribute and collect data to and from a matrix of DSP ASSPs
• Using the FPGA as a coprocessor or custom peripheral to a DSP
• Using embedded soft CPUs and the parallel DSP processing structures within the FPGA to eliminate the DSP ASSPs

Let us take a deeper look at each processing option, as can be seen in Figure 1.

The DSP matrix
In general, CAT scanners and similar diagnostic instruments collect huge amounts of data, requiring extremely complex algorithms to convert the data into meaningful images. Traditionally, DSPs have been used to process these algorithms. In a DSP ASSP approach, engineers have only two options to increase performance:

• Replace the DSP with a higher frequency model
• Rewrite portions of the software into pipelined assembly code

A third option, leveraging FPGAs, creates a DSP matrix where multiple DSPs are arrayed together to deliver parallel DSP processing. One or more FPGAs receive the entire data stream and distribute it between DSPs, which perform the system-state machine management, compute linear pixel-to-pixel increments in the projection plan, and control the memory-and-accumulate module. The processed pixels are then sent to another FPGA for final accumulation, image reconstruction, and output to monitor.

The core difficulty with using DSPs for all pixel processing relates to cost. DSPs are essentially serial machines, processing one element of the signal chain at a time. In the case of some high-end DSPs, a small number of instructions can be processed simultaneously providing a small degree of parallelization. However, the cost of these DSPs can be ten times that of a non-parallel version. Although multiple DSPs can be utilized to obtain higher parallel processing, the costs rise very quickly as the process is implemented. Software for these systems becomes much more complex, requiring a real-time operating system or very careful interprocessor communications schemes. However, the degree of true parallelism is still relatively low and comes at a significant price in terms of design time, cost of goods, and time-to-market.

Coprocessing
A better approach than using multiple DSPs, combines a DSP ASSP together with a FPGA. This approach leverages the existing code base of a single DSP software image with the massively parallel processor resources embedded within the FPGA. The DSP continues to execute the majority of the code including all complex control plane processing, allowing the FPGA to act as a custom peripheral or coprocessor to accelerate any process intensive code within the imaging algorithm, which can be seen in Figure 2. When the DSP ASSP gets to a process intensive section of code, it instructs the coprocessor to gather the data stored within the memory space via direct memory access, process the image and notify the DSP ASSP, when it completes its task.

Today’s FPGAs have distributed banks of DSP blocks containing multitudes of multipliers and accumulators. The key to hardware acceleration is to leverage these DSP resources by finding software loops in the algorithm which can be made massively parallel. However, DSP blocks alone are not sufficient to accelerate performance. In medical imaging applications, such as CAT scanner and Magnetic Resonance Imaging (MRI) equipment, the input data consists of large blocks of scanned image projections residing in memory. The distributed and aggregated blocks of memories in FPGAs enable the large blocks of image data to be processed concurrently within the DSP blocks.

Finally the use of reconfigurable logic and routing elements, the core building blocks within an FPGA, integrates all the parallel memory blocks and DSP elements together into an imaging co-processing engine. These FPGA features provide the ultimate flexibility necessary to create parallel processing engines for any imaging algorithm and performance far beyond that of DSP ASSPs alone. Many equipment designers have converted a cascaded set of operations in a DSP requiring thousands of clock cycles into a parallel FPGA structure which operates in a few clock cycles at +200 MHz, at least a two order of magnitude improvement.

FPGA alone
With today’s capability to instantiate one or more soft CPUs within the FPGA resources (soft CPUs utilize only a portion of logic resources and thus multiple copies can be placed anywhere within the FPGA), the entire DSP function can be integrated in a single device. The complex control plane software in C can be ported to one FPGA CPU, while other custom peripherals and CPUs act as slave processors.

There are three primary methods of hardware acceleration within the FPGA:

1. Custom Processor (CusP) or Application Specific Instruction Processor (ASIP) is software programmed processor consisting of building block functions with reconfigurable interconnections between the blocks
2. Custom instruction(s) using hardware extensions of the soft CPU instruction set, such as a floating-point instruction implemented in hardware
3. Custom peripheral or coprocessor (can be used with internal or external CPU) as described above

These methods are described and implemented in much more detail and in our references. A quick summary of the performance metrics of the three methods executing the same algorithm is shown in Table 1. Note the ASIP provides similar performance to a GPP with an implementation which is smaller and more power efficient in an FPGA.

While conceptually hardware acceleration sounds easy, tying together multiple processors and peripherals into an efficient architecture can be a time and resource consuming endeavor without advanced FPGA system building tools. Ultimately, the use massive hardware acceleration in FPGA technology justifies the effort, providing lower system costs and much faster image processing, benefiting both physicians and patients.

System benefits
The flexibility of FPGA capabilities helps designers create systems that were previously impossible due to time-to-market issues, prohibitive cost-of-goods, or traditional DSPs could not handle the computational load. FPGAs offer additional functionality, faster execution speeds, and lower power requirements than DSP only solutions, not to mention declining cost. These factors enable medical equipment manufacturers to take advantage of highly optimized silicon without having to assume the expense and risk of developing an ASIC, which can add many months to a product design schedule.

A growing advantage of an FPGA-based system is that engineers can upgrade features by sending software and hardware improvements. This is possible because FPGA technology is reconfigurable at anytime during development, production or even in the field. The ability to upgrade an expensive piece of medical imaging equipment by a simple file transfer means a longer time-in-market for instru ment manufacturers and cost savings for healthcare establishments needing to replace equipment. For patients, this advance means more timely access to the best possible diagnosis and treatment.

For these reasons, equipment manufacturers are increasingly relying on programmable logic to provide the flexibility required to respond to shifting market demands, while maintaining the necessary cost and performance requirements. This reliance is reflected in the growth rate of FPGAs within medical imaging equipment, which is double that of the systems themselves.

Conclusion
FPGA vendors are directing major efforts to address DSP applications for medical imaging. Consequently, FPGA solutions will increasingly provide the processing power new medical imaging applications require to handle challenges such as ultra-high signal processing performance, very-high memory bandwidth, and increased interconnectivity between processing elements. The complementary capabilities of DSPs and FPGAs integrated into medical imaging systems will continue to enable designers to deliver lower equipment cost and better image resolution for tomorrow’s health providers.

References

1. Mehta, Tapan A., FPGA Co-Processing Solutions for High-Performance Signal Processing Applications, GSPx, September 27, 2004.
2. Seely, Joel A., Using Hardware Acceleration Units in Software Defined Radio Modem Functions, COTS Journal, January 14, 2005.
3. Sidhu, Adesh, Programmable Logic Devices offer co processor muscle for high bandwidth image processing Part I and II, Planet Analog, September 10, 2003.

. . . . .

Charlie Jenkins is Senior Technical Marketing Manager, Test and Medical Business Unit, Altera Corporation. He joined Altera in 2004 to provide an in-depth technical understanding of the varied equipment and devices within the test and medical markets. Charlie has more than 15 years of semiconductor experience spanning engineering, applications, sales, marketing, and business development responsibilities. Before joining Altera, he was the vice president of marketing for several NPU startups and senior applications manager/FAE at NEC and GEC-Plessey, focusing in wired/wireless communications IP, SERDES, and FPGAs. Previously, Charlie held design and application engineering positions at Coherent Medical Systems, Pro-Log, and IBM. Charlie holds a master of science degree in electrical engineering and a bachelor of science degree in electrical engineering from the University of Louisville.

For more information about Altera, visit www.altera.com.

]]> http://tech.opensystemsmedia.com/dsp/2005/11/the-dsp-solution-spectrum-for-medical-imaging-applications-using-fpgas/feed/ 0 http://www.dsp-fpga.com/articles/id/?51 http://www.dsp-fpga.com/articles/id/?51#comments Sun, 13 Nov 2005 15:00:00 +0000 Brian Jentz, Altera http://tech.opensystemsmedia.com/dsp/?guid=f4e758e59c9dad05130e8dd019c5ef83

High throughput and design flexibility have positioned FPGAs as a solid silicon solution over traditional DSP devices in high-performance DSP applications like mobile base stations, medical imaging, and document imaging. In many cases, high density ASICs and DSPs appear on the same board as the FPGA. Hardware tasks, traditionally partitioned between the ASIC and FPGA, now primarily fall to FPGAs, which provide a cost-effective alternative for DSP implementation that easily can be adopted for a broad range of applications. This article tells how.

High throughput and design flexibility have positioned FPGAs as a solid silicon solution over traditional DSP devices in high-performance DSP applications like mobile base stations, medical imaging, and document imaging. In many cases, high density ASICs and DSPs appear on the same board as the FPGA. Hardware tasks, traditionally partitioned between the ASIC and FPGA, now primarily fall to FPGAs, which provide a cost-effective alternative for DSP implementation that easily can be adopted for a broad range of applications. This article tells how.

Standard-cell ASICs usually were chosen for their performance, density, complex logic designs, and cost-per-unit benefits. However, these same ASICs also increase time to market, have high development costs, and represent considerable financial risk if feature requirements change or the product doesn’t hit expected volume levels.

For example, many companies suffered significant financial setbacks developing ASICs for DSP functionality as part of the cellular base station development for the 3rd Generation Partnership Program (3GPP) standard; the culprits proved to be significant development changes in the standard as it was being established.

In addition to higher throughput and flexibility, FPGAs provide more raw data processing power than traditional DSP processors. Since FPGAs can be reconfigured in hardware, they offer complete hardware customization while implementing various DSP applications. FPGAs also boast features critical to key DSP applications, such as embedded memory, DSP blocks, and embedded processors (see Figure 1).

FPGAs manufactured with 90 nm technology provide up to 96 embedded DSP blocks, delivering 384 18 x 18 multipliers operating at 420 MHz. This equates to over 160 giga multiplies per second throughput – a performance improvement of over 30 times what is provided with the fastest DSPs on the market today. This configuration leaves the programmable logic elements on the FPGAs available to implement additional signal processing functions and system logic, including high-speed interfaces such as RapidIO and external memory interfaces like DDR2 controllers. With up to 8 Mb of high bandwidth embedded memory, FPGAs can eliminate the need for external memory in certain cases.

DSP development flow with structured ASICs
Structured ASICs, which represent the middle ground between FPGAs and standard-cell ASIC design solutions, are another reason developers are rethinking their use of traditional ASICs in high-performance, high-volume DSP applications. Structured ASICs deliver standard-cell ASIC-like performance and power consumption at unit costs better than FPGAs by an order of magnitude, but at very low total development costs. From a silicon perspective, they closely resemble FPGAs in terms of prefabricated base arrays with predefined logic, memory, clock networks, and I/O resources for a given device. The latest generation of structured ASICs, manufactured in 90 nm process technology, offer up to 2.2 M ASIC gates for logic and DSP, an additional 1.4 M gates dedicated for DSP Blocks, and 8.8 Mb of memory.

The same DSP development flow used to target FPGAs, including standard synthesis, verification, timing analysis, and equivalency checking tools is applicable to structured ASICs. This development flow provides system-level integration and flexibility for hardware and software partitioning of the DSP system. In addition, development tools can be combined to provide a complete design platform that allows the user to reap the benefits of performance and flexibility of a combined hardware and software implementation in a single system.

Complete DSP system design for structured ASICs requires both high-level algorithm and Hardware Description Language (HDL) development tools. The last several years has seen rapid adoption of MATLAB/Simulink-based tools targeted for FPGA and structured ASIC implementation. This integration enables system, algorithm, and hardware designers to share a common development platform, reducing time to market. Algorithmic intellectual property (IP), such as MPEG4, JPEG2000, and H.264 Video Compression and Forward Error Correction for WiMAX, has been optimized for FPGAs and structured-ASICs, enabling a further reduction in time to market.

However, if the proven original FPGA design is not used as the structured ASIC moves into high-volume production, the development process presents the same degree of risk as that of a standard-cell ASIC. To minimize risks, the design methodology must support seamless migration from the FPGA prototype to the structured ASIC (see Figure 2). Also, the system should support the FPGA with structured ASIC pin-to-pin compatibility. This eliminates re-spinning the design and schedule pressure from redeveloping and revalidating the system, resulting in significant cost savings and aforementioned time-to-market benefits.

Conclusion
Previously, developers were forced to use standard-cell ASICs to hit their price, space, and performance targets. In today’s market, however, increasing competitive pressures and shorter product life cycles give designers less time to develop and differentiate higher performance, and more complex designs usually requiring long verification and simulation cycles. With prices as low as $15, densities up to 2.2 M ASIC gates and 350 MHz system performance, structured ASICs offer developers a compelling alternative to standard-cell ASICs, enabling them to minimize design risk, reduce development costs, and shorten time-to-market costs across a wide variety of DSP applications.

. . . . .

Brian Jentz is Altera’s DSP Marketing Manager. He joined the company in October 2000 and is responsible for new product definition and marketing of DSP products. Before joining Altera, Brian spent seven years at Texas Instruments, most recently as a DSP product specialist. He holds a BSEE from Purdue University and has completed course work towards an MSEE at Georgia Tech.

For more information about Altera, visit www.altera.com.

]]> http://tech.opensystemsmedia.com/dsp/2005/11/leveraging-structured-asics-for-signal-processing-applications/feed/ 0 http://www.dsp-fpga.com/articles/id/?72 http://www.dsp-fpga.com/articles/id/?72#comments Sat, 01 Oct 2005 15:00:00 +0000 Sumit Mitra, Microchip Technoloigy http://tech.opensystemsmedia.com/dsp/?guid=c40dea418547ee125ddbd6d1ddbd60a2

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