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	<title>DSP &#187; Video</title>
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	<description>Digital Signal Processing (DSP) is the method of processing signals and data in order to enhance or modify those signals or to analyze those signals to determine specific information content.  A typical DSP system consists of a processor and other hardware used to convert outside analog signals to digital form and possibly back to analog (continuous) form. The DSP TechChannel delivers news, discussion, analysis, and resources related to digital signal processing.</description>
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		<title>ESC / Design West demo from Xilinx Booth #1708</title>
		<link>http://www.youtube.com/watch?v=BBFBHraToR0&#038;feature=youtube_gdata</link>
		<comments>http://www.youtube.com/watch?v=BBFBHraToR0&#038;feature=youtube_gdata#comments</comments>
		<pubDate>Thu, 12 Apr 2012 20:10:44 +0000</pubDate>
		<dc:creator>Patrick Hopper</dc:creator>
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		<description><![CDATA[Xilinx #Booth 1708 at ESC / Design West.  Xilinx Zynq - 7000 EPP and FPGAs]]></description>
			<content:encoded><![CDATA[<p>Xilinx #Booth 1708 at ESC / Design West.  Xilinx Zynq &#8211; 7000 EPP and FPGAs</p>
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		<title>MAXADCLite</title>
		<link>http://www.youtube.com/watch?v=fTSmpWIfUv4&#038;feature=youtube_gdata</link>
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		<pubDate>Thu, 29 Dec 2011 20:20:03 +0000</pubDate>
		<dc:creator>MaximIntProd</dc:creator>
				<category><![CDATA[Video]]></category>
		<category><![CDATA[MAXADCLite]]></category>

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		<description><![CDATA[Please Note: SPI is a trademark of Motorola, Inc.]]></description>
			<content:encoded><![CDATA[<p>Please Note: SPI is a trademark of Motorola, Inc.</p>
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		<title>Zynq-7000 Extensible Processing Platform Overview Video</title>
		<link>http://www.youtube.com/watch?v=zmlKvlKfU7Y&#038;feature=youtube_gdata</link>
		<comments>http://www.youtube.com/watch?v=zmlKvlKfU7Y&#038;feature=youtube_gdata#comments</comments>
		<pubDate>Wed, 31 Aug 2011 19:21:17 +0000</pubDate>
		<dc:creator>XilinxInc</dc:creator>
				<category><![CDATA[Video]]></category>
		<category><![CDATA[ARM]]></category>
		<category><![CDATA[Extensible]]></category>
		<category><![CDATA[Platform]]></category>
		<category><![CDATA[Processing]]></category>
		<category><![CDATA[Zynq]]></category>

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		<description><![CDATA[Vidya Rajagopalan, VP of Processing Platforms at Xilinx, and Dipesh Patel, VP of Technology, Physical IP Division at ARM, introduce the Zynq-7000 Extensible Processing Platform from Xilinx. This new class of product combines an industry-standard ARM® ...]]></description>
			<content:encoded><![CDATA[<p>Vidya Rajagopalan, VP of Processing Platforms at Xilinx, and Dipesh Patel, VP of Technology, Physical IP Division at ARM, introduce the Zynq-7000 Extensible Processing Platform from Xilinx. This new class of product combines an industry-standard ARM® dual-core Cortex™-A9 MPCore™ processing system with Xilinx unified 28nm architecture.</p>
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		<title>Pentek_7852_Demo_1.wmv</title>
		<link>http://www.youtube.com/watch?v=mwphhPHpDaw&#038;feature=youtube_gdata</link>
		<comments>http://www.youtube.com/watch?v=mwphhPHpDaw&#038;feature=youtube_gdata#comments</comments>
		<pubDate>Wed, 31 Aug 2011 18:28:52 +0000</pubDate>
		<dc:creator>worldmountainsea</dc:creator>
				<category><![CDATA[Video]]></category>
		<category><![CDATA[DDC.]]></category>
		<category><![CDATA[Digital Receiver]]></category>
		<category><![CDATA[http://gdata.youtube.com/schemas/2007#playlist]]></category>
		<category><![CDATA[Tech]]></category>

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		<description><![CDATA[Pentek Digital Receiver Demo Video; 4Ch ADC w/ 32Ch DDC, each DDC channel individually tunable. for more info, go to www.pentek.com or www.DynamicC4.com .]]></description>
			<content:encoded><![CDATA[<p>Pentek Digital Receiver Demo Video; 4Ch ADC w/ 32Ch DDC, each DDC channel individually tunable. for more info, go to www.pentek.com or www.DynamicC4.com .</p>
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		<title>Pentek_7852_Demo_1.wmv</title>
		<link>http://www.youtube.com/watch?v=mwphhPHpDaw&#038;feature=youtube_gdata</link>
		<comments>http://www.youtube.com/watch?v=mwphhPHpDaw&#038;feature=youtube_gdata#comments</comments>
		<pubDate>Wed, 31 Aug 2011 18:28:52 +0000</pubDate>
		<dc:creator>worldmountainsea</dc:creator>
				<category><![CDATA[Video]]></category>

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		<description><![CDATA[Pentek Digital Receiver Demo Video; 4Ch ADC w/ 32Ch DDC, each DDC channel individually tunable. for more info, go to www.pentek.com or www.DynamicC4.com .]]></description>
			<content:encoded><![CDATA[<p>Pentek Digital Receiver Demo Video; 4Ch ADC w/ 32Ch DDC, each DDC channel individually tunable. for more info, go to www.pentek.com or www.DynamicC4.com .</p>
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		<title>First Xilinx Virtex-7 FPGA Demonstration</title>
		<link>http://www.youtube.com/watch?v=hWyV09Ffo1U&#038;feature=youtube_gdata</link>
		<comments>http://www.youtube.com/watch?v=hWyV09Ffo1U&#038;feature=youtube_gdata#comments</comments>
		<pubDate>Wed, 31 Aug 2011 18:28:52 +0000</pubDate>
		<dc:creator>XilinxInc</dc:creator>
				<category><![CDATA[Video]]></category>
		<category><![CDATA[28nm;]]></category>
		<category><![CDATA[FPGA;]]></category>
		<category><![CDATA[Semiconductor]]></category>
		<category><![CDATA[Xilinx;]]></category>

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		<description><![CDATA[Watch demonstration of the second device in the Xilinx 28nm FPGA family -- the high performance Virtex-7 XV485T.]]></description>
			<content:encoded><![CDATA[<p>Watch demonstration of the second device in the Xilinx 28nm FPGA family &#8212; the high performance Virtex-7 XV485T.</p>
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		<title>Pentek_7852_Demo_2.wmv</title>
		<link>http://www.youtube.com/watch?v=QQ4Q7PB28B4&#038;feature=youtube_gdata</link>
		<comments>http://www.youtube.com/watch?v=QQ4Q7PB28B4&#038;feature=youtube_gdata#comments</comments>
		<pubDate>Wed, 31 Aug 2011 18:28:52 +0000</pubDate>
		<dc:creator>worldmountainsea</dc:creator>
				<category><![CDATA[Video]]></category>
		<category><![CDATA[DDC]]></category>
		<category><![CDATA[Digital]]></category>
		<category><![CDATA[Receiver]]></category>
		<category><![CDATA[SDR]]></category>

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		<description><![CDATA[Pentek Digital Receiver Demo Video. For more info go to www.Pentek.com or www.DynamicC4.com]]></description>
			<content:encoded><![CDATA[<p>Pentek Digital Receiver Demo Video. For more info go to www.Pentek.com or www.DynamicC4.com</p>
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		<title>Pentek_8Ch_Beamforming_System.wmv</title>
		<link>http://www.youtube.com/watch?v=G0wsEJ_BeQw&#038;feature=youtube_gdata</link>
		<comments>http://www.youtube.com/watch?v=G0wsEJ_BeQw&#038;feature=youtube_gdata#comments</comments>
		<pubDate>Wed, 31 Aug 2011 18:28:52 +0000</pubDate>
		<dc:creator>worldmountainsea</dc:creator>
				<category><![CDATA[Video]]></category>
		<category><![CDATA[8Ch]]></category>
		<category><![CDATA[Beamforming]]></category>
		<category><![CDATA[System]]></category>

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		<description><![CDATA[Pentek's 8Ch Beamforming Demo System. For more info, please visit www.pentek.com or www.DynamicC4.com .]]></description>
			<content:encoded><![CDATA[<p>Pentek&#8217;s 8Ch Beamforming Demo System. For more info, please visit www.pentek.com or www.DynamicC4.com .</p>
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		<title>Lattice ECP3 FPGA Jamz</title>
		<link>http://www.youtube.com/watch?v=gM2hnra55Hs&#038;feature=youtube_gdata</link>
		<comments>http://www.youtube.com/watch?v=gM2hnra55Hs&#038;feature=youtube_gdata#comments</comments>
		<pubDate>Wed, 31 Aug 2011 18:28:52 +0000</pubDate>
		<dc:creator>latticesemiconductor</dc:creator>
				<category><![CDATA[Video]]></category>
		<category><![CDATA[Cascadable DSP]]></category>
		<category><![CDATA[DDR3]]></category>
		<category><![CDATA[ECP3]]></category>
		<category><![CDATA[Embedded Memory Blocks]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[Lattice]]></category>
		<category><![CDATA[Low Power]]></category>
		<category><![CDATA[SERDES]]></category>
		<category><![CDATA[Smockie]]></category>

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		<description><![CDATA[Lattice ECP3 FPGA: Low Power, SERDES, DDR3, Cascadable DSP, Embedded Memory Blocks-- a Perfect Balance!
http://www.latticesemi.com/ecp3jamz]]></description>
			<content:encoded><![CDATA[<p>Lattice ECP3 FPGA: Low Power, SERDES, DDR3, Cascadable DSP, Embedded Memory Blocks&#8211; a Perfect Balance!</p>
<p>http://www.latticesemi.com/ecp3jamz</p>
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