MathWorks Inc.  has announced HDL Coder for MATLAB, a tool that enables algorithm developers and system engineers to  automatically generate synthesizable VHDL and Verilog code from models they have written in the company's MATLAB language.  Engineers can use the tool, which was previously available only in MathWorks Simulink, to implement FPGA[] programming or for ASIC prototyping and design.

According to Ken Karnofsky, Senior Strategist at The MathWorks, Inc., HDL Coder provides a missing link from system-level algorithmic design, to the typically disparate hardware design and verification flows that are supported by traditional EDA[] tools.  Features of HDL Coder include automatic floating-point to fixed-point conversion, HDL resource optimizations and reports, algorithm-to-HDL traceability - often required for DO-254 compliance, and integration with popular simulation and synthesis tools.

The HDL Workflow Advisor Graphical User Interface (GUI) for HDL Coder, provides options to customize and optimize HDL code, and guides users through each step in the process (left-side column in the figure above) to automatically program FPGAs directly from MATLAB.

As a complement to HDL Coder, MathWorks is introducing HDL Verifier (formerly known as EDA Simulator Link), with capabilities for Simulink/MATLAB co-simulation with Verilog/VHDL simulators, such as Mentor Graphics' ModelSim and Cadence's Incisive.  HDL also provides for FPGA-in-the-loop verification,   and currently supports a total of fifty FPGA evaluation boards from Altera and Xilinx.

Pricing and Availability:

HDL Coder and HDL Verifier are available immediately.

• Single-user U.S. list prices for HDL Coder start at $10,000.  More information is available on the MathWorks product Web site: www.mathworks.com/products/hdl-coder.
• U.S. list prices for HDL Verifier start at $3,250. More information is also available on the MathWorks product Web site: www.mathworks.com/products/hdl-verifier.