Verific Exhibits at 49th Design Automation Conference and Hosts DAC Tuesday Night Reception

May 23, 2012 — Verific Design Automation

WHO: Verific , supplier of industry-standard, IEEE-compliant SystemVerilog and parsers and elaborators

WHAT: Will exhibit at the 49th in booth #1807 and host the DAC Tuesday Night Reception

WHEN: Exhibits will be open Monday-Wednesday, June 4-6, from 9 a.m.-6 p.m. The Tuesday Night Reception will be held from 6-7 p.m.

WHERE: Moscone Center, South Hall, San Francisco. The Tuesday Night Reception will be held in Room 303/Outside Terrace.

WHY: Verific's DAC theme, "Build Your Own Register Transfer Level () Tools," invites computer-aided design (CAD) managers and system-on-chip (SoC) designers to find out how they can build their own internal RTL-based () tools with Verific's Perl application program interface (API).

Verific's software is also to be found in 32 other DAC exhibitor booths, serving as the front end to EDA and analysis, simulation, verification, synthesis, emulation and test tools. The Verific Parser Platform includes support for SystemVerilog, , VHDL and UPF.

For more details about Verific, visit www.verific.com.

Information on DAC can be found at www.dac.com.

 

About Verific Design Automation

 

Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides de facto standard front-end solutions supporting SystemVerilog, Verilog and VHDL design. Verific's software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: info@verific.com. Website: www.verific.com.

 

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