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Use Transaction-Level Models to ensure hardware and software are in sync
5 months ago — Michael McNamara, Cadence Design Systems
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Approaches and tools for FPGA mixed-signal integration
5 months ago — Allan Chin, Stellamar
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Virtual or real: Prototyping platform(s) for ARM-based FPGA design
5 months ago — Mike Demler, Editorial Director
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New developments in DSP design
5 months ago — Michael Parker, Altera Corporation
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DSP, FPGAs, and the quest for instant gratification
5 months ago — Mike Demler, Editorial Director
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Power is the common denominator, but greater analog design productivity is the solution
5 months ago — Mike Demler, Editorial Director
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EE Daily News 20-page special report reviews the EDA/IP exec panel at GTC2011
6 months ago — Mike Demler, EE Daily News
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FPGA design tools: Misconceived and missed opportunities
6 months ago — Jeff Jussel, Newark/element14
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FPGA verification must address user uncertainty for prototyping, system validation
6 months ago — Loring Wirbel, Footwasher Media
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FPGAs can lead the way to next-generation technology
7 months ago — Mike Demler, Editorial Director
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FPGA design tool vendor GateRocket has ceased operations
8 months ago — Mike Demler, EE Daily News
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Show me the money – the valuation of Apache Design Solutions
8 months ago — Mike Demler, EE Daily News
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Nanometer Circuit Verification Forum to follow CICC
8 months ago — Mike Demler, EE Daily News
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EDA acquisitions point the way to long-elusive growth
8 months ago — Mike Demler, Editorial Director
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Platforms continuum for system realization
May 05, 2011 — Ran Avinun, Cadence Design Systems
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EDA Consortium: Accomplishing together that which we cannot do as individual companies
November 12, 2010 — Robert Gardner, EDA Consortium
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New paradigm speaks volumes for Knowles MEMS microphone design
November 12, 2010 — Pete Loeppert, PhD, Knowles Electronics
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Green in: Power-saving DSP core, noise-adapting PLC chip, and a low-power EDA design flow
September 16, 2010 — Don Dingee
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Bringing the programmable imperative to space
August 12, 2010 — Chris A. Ciufo, Editor
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Using emulation to verify today’s complex designs
June 14, 2010 — Lauro Rizzatti, EVE-USA
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Monitor opens an eye to high-speed SERDES performance
November 13, 2009 — Kevin Walsh, Snowbush IP, a division of Gennum
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Enabling better testing: Reprogrammable on-chip instrumentation
November 09, 2009 — Paul Bradley, DAFCA
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DO-254: The other safety-critical specification
May 16, 2009 — Chris A. Ciufo, Editor
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FPGA synthesis tools meet the DO-254 challenge
April 20, 2009 — Sanjay Thatte, Mentor Graphics Corporation
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Tipping points in programmable logic: Is FPGA design more complex than ASIC design?
December 02, 2008 — Andrew Dauman, Synopsysí Synplicity Business Group
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OVP makes system-level virtual prototyping a reality
July 15, 2008 — Brian Bailey, Imperas
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Modeling techniques maximize value of virtual platforms
July 15, 2008 — Andy Ladd, Carbon Design Systems
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Zooming in on MEMS designs with EDA
May 29, 2008 — Staff, OpenSystems Media
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Living on borrowed time: Oregonís 1960s era public safety radio nets ready for upgrades
January 03, 2008 — Mike Zanon, Oregon Wireless
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OSP editors weigh in on programmable logic
May 01, 2007 — Chris A. Ciufo, Editor, OpenSystems Media

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EDA // Articles

Use Transaction-Level Models to ensure hardware and software are in sync

Approaches and tools for FPGA mixed-signal integration

Virtual or real: Prototyping platform(s) for ARM-based FPGA design

New developments in DSP design

DSP, FPGAs, and the quest for instant gratification

Power is the common denominator, but greater analog design productivity is the solution

EE Daily News 20-page special report reviews the EDA/IP exec panel at GTC2011

FPGA design tools: Misconceived and missed opportunities

FPGA verification must address user uncertainty for prototyping, system validation

FPGAs can lead the way to next-generation technology

FPGA design tool vendor GateRocket has ceased operations

Show me the money – the valuation of Apache Design Solutions

Nanometer Circuit Verification Forum to follow CICC

EDA acquisitions point the way to long-elusive growth

Platforms continuum for system realization

EDA Consortium: Accomplishing together that which we cannot do as individual companies

New paradigm speaks volumes for Knowles MEMS microphone design

Green in: Power-saving DSP core, noise-adapting PLC chip, and a low-power EDA design flow

Bringing the programmable imperative to space

Using emulation to verify today’s complex designs

Monitor opens an eye to high-speed SERDES performance

Enabling better testing: Reprogrammable on-chip instrumentation

DO-254: The other safety-critical specification

FPGA synthesis tools meet the DO-254 challenge

Tipping points in programmable logic: Is FPGA design more complex than ASIC design?

OVP makes system-level virtual prototyping a reality

Modeling techniques maximize value of virtual platforms

Zooming in on MEMS designs with EDA

Living on borrowed time: Oregonís 1960s era public safety radio nets ready for upgrades

OSP editors weigh in on programmable logic

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