Mark Horowitz, chairman of Stanford University’s Electrical Engineering Department, will offer a look at Digital Analog Design during the 49th Design Automation Conference (DAC), as part of the IEEE Council on Electronic Design Automation (CEDA) Distinguished Speaker Series.

The talk will be held during lunch Tuesday, June 5, from 11:45 a.m.-1:30 p.m. in Room #303 at the Moscone Center in San Francisco. It is open to all DAC attendees on a first-come, first-served basis.

In his talk, Professor Horowitz will describe the advances in digital design tools over the last 30 years, contrasting the more modest progress in analog tools. He will illustrate digital tools’ use of abstractions to allow them to validate that implementations match functional models and that the composition of cells matches the composition of the functional models. Professor Horowitz will explain why this is more difficult for analog circuits and outline how it can be done by illustrating ways to formally validate analog models, define analog fault models, and efficiently explore the effect of process variations.

In addition to his role as department chair, he is the Yahoo! Founders Professor at Stanford University and a founder of Rambus, Inc. Professor Horowitz is a fellow of IEEE and ACM and is a member of the National Academy of Engineering and the American Academy of Arts and Science. Dr. Horowitz’s research interests span using electrical engineering and computer science analysis methods to problems in molecular biology to creating new design methodologies for analog and digital VLSI circuits. He received Bachelor of Science and Master of Science degrees in Electrical Engineering from MIT, and a Ph.D. from Stanford.

Professor Horowitz’s talk is organized by Joel Phillips of Cadence Design Systems and Technical Activities chair for CEDA. To learn more about CEDA and its Distinguished Speaker Series or details, go to: www.c-eda.org.

Details on this year’s DAC can be found at: www.dac.com.

About the IEEE Council on EDA

The IEEE Council on Electronic Design Automation (CEDA) provides a focal point for EDA activities spread across six IEEE societies (Antennas and Propagation; Circuits and Systems; Computer; Electron Devices; Microwave Theory and Techniques; and Solid State Circuits). It sponsors more than 12 conferences, including the Design Automation Conference (DAC), International Conference in CAD (ICCAD) and Design Automation and Test in Europe (DATE). CEDA publishes IEEE Transactions on CAD and the IEEE Embedded Systems Letters. CEDA is increasingly involved in recognizing its leaders via the A. Richard Newton Award, Early Career Award and Phil Kaufmann Award. CEDA welcomes volunteers and local chapters. For more information, go to: www.c-eda.org.

The IEEE Council on Electronic Design Automation (CEDA) will present four achievement awards and three newly appointed Fellows of the IEEE during the opening session of the 49th Design Automation Conference (DAC) Tuesday, June 5, at the Moscone Center in San Francisco.

The awards are the Donald O. Pederson for the best paper of IEEE Transactions on Computer-Aided Design, the A. Richard Newton Technical Impact, the Outstanding Service Contribution and the Phil Kaufman.

“It gives me great pleasure to announce this year’s award recipients, all of whom have made lasting contributions to our industry,” says David Yeh, director, Integrated Circuit and Systems Sciences at Semiconductor Research Corporation and chair of the CEDA Awards Committee. “We’re also delighted to be able to honor three Fellows of the IEEE from within the CEDA Community. Please join us at DAC as we honor them.”

The Donald O. Pederson Award recognizes the best paper of IEEE Transactions on Computer-Aided Design titled, “An Analytical Approach for Network-on-Chip Performance Analysis,” from the December 2010 issue. This year’s recipients are co-authors Umit Ogras, currently at Intel, Paul Bogdan, post-doctoral fellow at Carnegie Mellon University (CMU), and Radu Marculescu, professor of electrical and computer engineering at CMU.

The A. Richard Newton Technical Impact Award in Electronic Design Automation co-sponsored by CEDA and the ACM Special Interest Group on Design Automation (SIGDA) will be presented to Altan Odabasioglu, founder of Gear Design Solutions, EDA Technologist Mustafa Celik, and Larry Pileggi, Tanoto professor at CMU. They co-authored “PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm,” published in the August 1998 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

The IEEE CEDA Outstanding Service Contribution Award will be presented to past DAC General Chair Leon Stok, vice president of EDA at IBM.

The session will feature the presentation of the Phil Kaufman Award to Dr. C. L. David Liu, the William Mong honorary chair professor of Computer Science and former president of the National Tsing Hua University in Hsinchu, Taiwan. The yearly award, originally presented at ICCAD in 2011, is sponsored by CEDA and the Electronic Design Automation Consortium.

The three Fellows of the IEEE from CEDA to be honored are Naehyuck Chang from Seoul National University, Luis Silveira from the Technical University of Lisbon and Stephen Trimberger of Xilinx, Inc.

For more information on CEDA, go to www.c-eda.org.

Details on this year’s DAC can be found at www.dac.com.

About the IEEE Council on EDA

The IEEE Council on Electronic Design Automation (CEDA) provides a focal point for EDA activities spread across six IEEE societies (Antennas and Propagation; Circuits and Systems; Computer; Electron Devices; Microwave Theory and Techniques; and Solid State Circuits). It sponsors more than 12 conferences, including the Design Automation Conference (DAC), International Conference in CAD (ICCAD) and Design Automation and Test in Europe (DATE). CEDA publishes IEEE Transactions on CAD and the IEEE Embedded Systems Letters. CEDA is increasingly involved in recognizing its leaders via the A. Richard Newton Award, Early Career Award and Phil Kaufmann Award. CEDA welcomes volunteers and local chapters. For more information, go to: www.c-eda.org.

The Verilog2VHDL tool now supports the following Verilog 2005 constructs: multi-dimensional arrays, signed regs and nets that convert to VHDL numeric_std.signed data types, Verilog 2005 event control expressions such as @(posedge foo, posedge bar), the new localparam keyword, module parameter port lists, and named parameter assignments.

The VHDL2Verilog tool also received several enhancements including better generation of bit ranges for parameters generated from VHDL constants and an option to translate VHDL integer literals into fixed-length bit strings for synthesized designs.

** HDL Debugging Support ** 

The V2V tools are stand-alone command-line programs, but SynaptiCAD’s graphical HDL debugger, BugHunter Pro, can also be used to configure options to the translators and launch them on files in an HDL design project. Using BugHunter in combination with the V2V tools, users can quickly translate a design, then compile and simulate both the original files and the translated files to compare their output, make any necessary corrections, then resimulate. The BugHunter debugger is compatible with the following VHDL and Verilog simulators: SynaptiCAD’s Verilogger Extreme, Cadence’s Incisive, Synopsys VCS, Mentor Graphic’s ModelSim, and Aldec’s ActiveHDL.

** Translation Service ** 

SynaptiCAD will also perform translation of HDL code as service, using their translators to do the bulk of the work, then making manual corrections as necessary. SynaptiCAD particularly recommends this service for designers who are not fluent in both Verilog and VHDL coding. The cost of the translation service typically depends on the size of the IP to be translated.

** Pricing and Availability ** 

The V2V translation software is available on Windows and Linux. The software can be licensed on either a permanent or leased basis, and both floating and node-locked versions are available. For more information, contact SynaptiCAD via phone: (800)804-7073 or (540)953-3390, email: sales@syncad.com, or the web: www.syncad.com.

Oasys Design Systems, a provider of chip design software, today announced it has closed Series B Funding with investments from Intel Capital, Intel’s global investment organization, and Xilinx, a leading provider of programmable platforms. Funding will be used as working capital to expand Oasys’ research and development team, as well as for further expansion of its worldwide support structure.

Chip Synthesis™ is a fundamental shift in how synthesis is applied to the design and implementation of integrated circuits (ICs). Traditional block-level synthesis tools do a poor job of handling chip-level issues. Oasys’ RealTime Designer™ is the first design tool for physical register transfer level (RTL) synthesis of 100-million gate designs and produces better results in a fraction of the time needed by traditional logic synthesis products. It features a unique RTL placement approach that eliminates unending design closure iterations between synthesis and layout.

“Xilinx has licensed Oasys technology and achieved excellent results across a wide range of designs,” says Salil Raje, vice president of Software and IP Product Development at Xilinx. “We have a long-standing and productive working relationship with the Oasys team and we are pleased to extend our support through this investment.”

“Oasys’ technology has the potential to positively impact the design flow for VLSI chip implementation,” adds Shishpal Rawat, director, Business Enabling Programs at Design Technology Solutions Group, Intel. “This is a new way of thinking for next-generation chip design implementation. We are pleased to invest in Oasys.”

“We are excited to have the venture capital arm of the number one semiconductor company and the number one programmable platforms vendor as investors in Oasys,” remarks Paul van Besouw, Oasys’ president and chief executive officer. “With tapeouts at 45- and 28-nanometer process nodes, Realtime Designer is the proven synthesis solution offering substantial runtime and capacity advantages for some of the world’s most complex designs. Intel Capital and Xilinx have given us strategic support, and their investment will enable us to scale commercially and to continue to advance our technology.”

Previously, Oasys announced that several top U.S. semiconductor companies, such as Texas Instruments, Qualcomm and Xilinx, are already using RealTime Designer. In 2011, Oasys enhanced its Chip Synthesis platform by adding design for test (DFT) capabilities and support for chip-level power design, further extending the fast speed and high capacity of RealTime Designer. These additional features completed the fully integrated Chip Synthesis design flow.

About Oasys Design Systems

Oasys Design Systems is a privately funded electronic design automation (EDA) software supplier with a revolutionary new platform called Chip Synthesis™, a fundamental shift in how synthesis is used to design and implement ICs larger than 20-million gates. It has attracted the support of legendary EDA leaders and its RealTime Designer™ product is in use at leading-edge semiconductor and systems companies worldwide. Corporate Headquarters is located at 3250 Olcott Street, Suite 120, Santa Clara, Calif. 95054. Telephone: (408) 855-8531. Facsimile: (408) 855- 8537. Email: info@oasys-ds.com. For more information, visit: www.oasys-ds.com.

Impulse Accelerated Technologies today announced an Arista Networks version of the Impulse C-to-FPGA optimizing compiler, in a kit providing everything needed for Arista users to compile their C algorithms to the FPGA integrated in Arista’s new 7124FX AppSwitch. Impulse C is a C-language development environment for FPGAs that allows software algorithms to be quickly and efficiently implemented in programmable hardware.

The Arista 7124FX AppSwitch is a 24-port 1/10-Gbps switch with hot-swappable redundant power supplies and fans packed into a 1RU box. What makes the 7124FX unique is the FPGA containing 6.2 million gates that are truly field programmable. The 7124FX is targeted at applications that can make use of high-capacity, low-latency logic in FPGAs at the network level, such as high-frequency trading, deep packet inspection, and media transcoding.

Where FPGA programming normally requires hardware design language (HDL) programming skills, the Impulse kit provides a means of compiling C code to the AppSwitch FPGA. In this tool flow, C algorithms can be expressed as streaming processes that are parallelized for acceleration of 10 to 100X, relative to CPU implementations. Impulse C can be used in conjunction with standard C development tools and debuggers, speeding the development and maintenance of algorithms requiring frequent updating.

Impulse C also facilitates the step-by-step validation from hardware-independent C-language to full hardware simulation, through integration with hardware simulators including ModelSim (from Mentor Graphics) or Active-HDL (available from Aldec, Inc.) Impulse C is the most widely accepted tool of this type, with a worldwide user base and over a decade of development.

Arista 7124FX AppSwitch platform support is provided in the Impulse compiler, speeding development time and reducing the need for hardware design expertise. The Impulse C AppSwitch development kit includes reference designs, Altera Quartus synthesis software, necessary drivers and even a programming cable: everything needed to get started programming the 7124FX.

Support from Impulse is available at multiple levels. The standard Impulse C kit for AppSwitch provides examples of “bump in the wire” processing, allowing software developers to more quickly refine their algorithms for FPGA parallelism. Beyond that, Impulse can also offer sample code and consulting to handle various exchange protocols, libraries of analytic functions and full-custom solutions. The 7124FX AppSwitch Development Kit is available through Arista Networks worldwide.

About Impulse

Founded in 2002, Impulse Accelerated Technologies provides software, IP, and training help application developers accelerate their algorithms in FPGA hardware. Impulse C is used worldwide by more design teams than any other C-to-FPGA toolset. Impulse users range from NASA, to Harvard, to Wall Street. www.ImpulseC.com.

Carbon Design Systems and Arteris, Inc., the inventor and leading supplier of network-on-chip (NoC) interconnect intellectual property (IP) solutions, announced today they have implemented a partnership agreement that enables accurate models of Arteris NoC interconnect IP to be generated, managed and distributed using the Carbon IP Exchange web portal.

The joint Carbon/Arteris solution offers design teams a way to easily create and import accurate Arteris FlexNoC interconnect models for Carbon SoCDesigner Plus.

“We see strong demand for models of Arteris’ NoC interconnect IP,” states Bill Neifert, chief technology officer at Carbon Design Systems®, the leading supplier of virtual platform and secure model solutions. “ARM’s Cortex-A15 and Cortex-A9 microprocessor designers are pushing for better price, performance and area tradeoffs and the SoC interconnect plays a vital role in serving this need. Our partnership with Arteris enables engineers to make architectural decisions and design tradeoffs based upon a 100%-accurate virtual representation.”

The new Carbon/Arteris flow allows Carbon’s SoCDesigner Plus users to use Arteris FlexNoC to configure their NoC interconnect fabric IP and then upload the configuration to Carbon IP Exchange. The web portal then creates a 100% accurate virtual model of the configuration and makes it available for download and use in SoCDesigner Plus.

“Simulation with virtual models of our NoC interconnect IP are the best way to make system-on-chip architectural optimizations and tradeoffs,” comments Kurt Shuler, Arteris’ vice president of marketing. “By partnering with Carbon to make 100% accurate models of our IP available on Carbon IP Exchange, we are empowering design teams to utilize virtual models earlier in the design process.”

Availability

Carbon’s 100% accurate models of Arteris FlexNoC interconnect IP are available now from the Carbon IP Exchange web portal.

About Carbon Design Systems

Carbon Design Systems offers the industry’s only unified virtual platform solution along with the leading solution for accurate IP model creation. Carbon virtual platforms can execute at 100s of MIPS and with 100% accuracy to enable application software development, detailed architectural analysis and secure IP model distribution. Carbon’s solutions are based on open industry standards, including SystemC, IP-XACT, Verilog, VHDL, OSCI TLM, MDI, CASI, CADI and CAPI. Carbon’s customers are systems, semiconductor and IP companies that focus on wireless, networking, and consumer electronics. Carbon is headquartered at 125 Nagog Park, Acton, Mass., 01720. Telephone: (978) 264-7300. Facsimile: (978) 264-9990. Email: info@carbondesignsystems.com. Website: www.carbondesignsystems.com.

About Arteris

Arteris, Inc. provides Network-on-Chip interconnect IP and tools to accelerate System-on-Chip semiconductor (SoC) assembly for a wide range of applications. Results obtained by using the Arteris product line include lower power, higher performance, more efficient design reuse and faster development of ICs, SoCs and FPGAs. Founded by networking experts, Arteris operates globally with headquarters in Sunnyvale, Calif., and an engineering center in Paris, France. Arteris is a private company backed by a group of international investors including ARM Holdings, Crescendo Ventures, DoCoMo Capital, Qualcomm Incorporated, Synopsys, TVM Capital, and Ventech. More information can be found at www.arteris.com.

SAN JOSE, CA–(Marketwire -03/06/12)- AT DATE Booth #2

WHO: Forte Design Systems™, a leading provider of software products that enable design at a higher level of abstraction and improve design results

WHAT: Will demonstrate Cynthesizer™ SystemC high-level synthesis used by design teams to reduce time-to-market pressures by designing at a higher level of abstraction at Design Automation & Test in Europe (DATE) 2012 in Booth #2

WHEN: March 13-15

WHERE: International Congress Centre in Dresden, Germany

To learn more about Forte and Cynthesizer, visit: www.ForteDS.com.

Details about this year’s DATE can be found at: www.date-conference.com/.

About Forte Design Systems

Forte Design Systems is a leading provider of software products that enable design at a higher level of abstraction and improve design results. Its innovative synthesis technologies and intellectual property offerings allow design teams creating complex electronic chips and systems to reduce their overall design and verification time. More than half of the top 20 worldwide semiconductor companies use Forte’s products in production today for ASIC, SoC and FPGA design. Forte is headquartered in San Jose, Calif., with additional offices in England, Japan, Korea and the United States. For more information, visit www.ForteDS.com.

According to Ken Karnofsky, Senior Strategist at The MathWorks, Inc., HDL Coder provides a missing link from system-level algorithmic design, to the typically disparate hardware design and verification flows that are supported by traditional EDA tools.  Features of HDL Coder include automatic floating-point to fixed-point conversion, HDL resource optimizations and reports, algorithm-to-HDL traceability – often required for DO-254 compliance, and integration with popular simulation and synthesis tools.

The HDL Workflow Advisor Graphical User Interface (GUI) for HDL Coder, provides options to customize and optimize HDL code, and guides users through each step in the process (left-side column in the figure above) to automatically program FPGAs directly from MATLAB.

As a complement to HDL Coder, MathWorks is introducing HDL Verifier (formerly known as EDA Simulator Link), with capabilities for Simulink/MATLAB co-simulation with Verilog/VHDL simulators, such as Mentor Graphics’ ModelSim and Cadence’s Incisive.  HDL also provides for FPGA-in-the-loop verification,   and currently supports a total of fifty FPGA evaluation boards from Altera and Xilinx.

Pricing and Availability:

HDL Coder and HDL Verifier are available immediately.

• Single-user U.S. list prices for HDL Coder start at $10,000.  More information is available on the MathWorks product Web site: www.mathworks.com/products/hdl-coder.
• U.S. list prices for HDL Verifier start at $3,250. More information is also available on the MathWorks product Web site: www.mathworks.com/products/hdl-verifier.

MOUNTAIN VIEW, CA– At DVCon 2012 Booth #1002

WHO: Breker Verification Systems, The System-on-Chip (SoC) Verification Company,

WHAT: Will demonstrate the latest version of TrekSoC™, the first commercially available software that automates the generation of self-verifying C test cases for multi-threaded SoC devices, at DVCon 2012 in Booth #1002 and sponsor the panel “Do We Have What It Takes for Full-SoC Verification?”

WHEN: The panel is Tuesday, February 28, from 7:30 to 8:30 a.m. and exhibits are Tuesday, February 28, from 3:30 to 6:30 p.m., and Wednesday, February 29, from 4:30 to 7 p.m.

WHERE: DoubleTree Hotel, San Jose, Calif.

The panel will be moderated by Brian Bailey, editor of EDA DesignLine for Electronic Engineering Times. Industry experts will answer questions from the audience regarding the best methods for verifying SoC designs.

The paper “Graph-IC Verification” will be presented by Dennis Ramaekers of ST-Ericsson, describing how the ST-Ericsson verification engineers used TrekSoC on a recent project. The paper is one of four to be presented during Session 8, “Getting to Coverage Closure,” Wednesday, February 29, from 8 a.m. to 10 a.m.

About Breker Verification Systems

Breker Verification Systems is an Electronic Design Automation (EDA) software company that provides innovative solutions to solve the challenge of complex system-on-chip (SoC) functional verification. Its TrekSoC™ software and unique SoC scenario-modeling™ approach are used in production at leading semiconductor companies in the U.S., Europe and India. Founded in 2003, it is privately held and funded, and based in Silicon Valley, Calif. Breker Verification Systems corporate headquarters are located at 800 West El Camino Real, Suite 180, Mountain View, Calif. 94040. Telephone: (650) 336-8872. Email: info@brekersystems.com. Website: www.brekersystems.com.

Louisville, CO – February 21, 2012 – With a well-earned reputation as the industry’s leading conference for the functional design and verification of electronic systems, organizers of this year’s Design and Verification Conference (DVCon) expect the program to be its most pertinent yet. Beginning next week, DVCon 2012 will provide attendees with valuable information applicable to today’s market conditions and technical challenges. The 20th annual Design and Verification Conference, sponsored by Accellera Systems Initiative, will be held February 27-March 1 at the DoubleTree Hotel in San Jose, California.

Highlights Discussed on Conversation Central

Conversation Central, the online radio show & podcast, featured DVCon 2012’s Technical Program Chair, Ambar Sarkar and Tutorials and Panels Chair, Stan Krolikoski last week to discuss why this year’s technical program is even better than the last. The two discussed what attendees can expect to learn and take away from the conference, as well as what they view as current and emerging trends. When asked why DVCon continues to grow in this economic climate, Sarkar responded, “In the face of one of the largest recessions, DVCon has gone from a three-day conference to four days. It is extremely relevant, participants are practicing engineers and the quality of papers is outstanding.” To listen to the podcast and get a preview of what you’ll see next week, visit blogs.synopsys.com/conversationcentral/2012/02/[...].

“If you are a systems, design, or verification engineer working on complex projects and products, you won’t want to miss DVCon 2012,” commented Karen Bartleson, DVCon General Chair. “Last year our survey of attendees indicated half want to learn about company-specific tools and the other half want to learn only pure technical content. We are able to provide both and give attendees options to choose which fit their needs best.”

The Industry Leaders panel, moderated by JL Gray of Verilab and “Cool Verification” will be held Tuesday, February 28th at 2:30pm in the Oak/Fir Ballroom. Titled, “The Resurgence of Chip Design,” Ted Vucurevich, Enconcert, Inc., John Costello, Altera Corp., Gary Smith, Gary Smith EDA, Victoria Coleman, Nokia and Jim Hogan, Vista Ventures LLC will discuss the trends influencing this change.

“Hearing about the challenges these industry influencers have faced and overcome should be of interest to all, whether you’re new to IC design and verification or a pro,” continued Bartleson. “I predict this panel will be ranked as one of the best panels ever assembled at DVCon. We hope to meet, and even surpass, your expectations with our outstanding program this year.”

The DVCon Expo will have a total of 34 exhibitors, including 7 first-timers. Exhibits will be open on Tuesday, February 28 3:30 – 6:30pm and Wednesday, February 29 from 4:30 – 7:00pm.

To view the complete 4 day program, including highlights of the Keynote, “Systemic Collaboration: Principles for Success in IC Design,” presented by Aart de Geus, Chairman and CEO of Synopsys, Inc. at 2:00pm on February 29th in the Oak/Fir Ballroom, as well as all of the technical sessions, poster sessions and sponsored tutorials, please visit the conference website www.dvcon.org.

Registration is available online. Complimentary registration is available for the exhibits, keynote and panels.

About DVCon

DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an industry consortium dedicated to the development and standardization of design and verification languages. For more information about Accellera, please visit www.accellera.org. For more information about DVCon, please visit www.dvcon.org. Follow @dvcon on Twitter or to comment, please use #dvcon.

WHO: EVE, the leader in hardware/software co-verification

WHAT: Will exhibit at DVCon 2012 in Booth #602

WHEN: Tuesday, February 28, from 3:30-6:30 p.m., and Wednesday, February 29, from 4:30-7 p.m.

WHERE: Doubletree Hotel, San Jose, Calif.

EVE will highlight at DVCon its new ZeBu-Blade2 hardware-assisted verification platform, the first member of the ZeBu emulation family based on Xilinx Virtex6-LX760 field programmable gate arrays (FPGAs). The desktop emulator supports full-chip application specific integrated circuit (ASIC) and system-on-chip (SoC) designs of up to 32-million ASIC gates. It offers fast execution and attractive pricing for best-in-class hardware/software integration ahead of silicon availability.

For more information about EVE and its hardware/software co-verification platforms, go to: www.eve-team.com.

DVCon details can be found at www.dvcon.org.

About EVE

EVE is the worldwide leader in hardware/software co-verification solutions, offering fast transaction-based co-emulation and in-circuit emulation, with installations at five of the top six semiconductor companies. EVE products shorten the overall verification cycle of complex integrated circuits and electronic systems designs. Its products can be integrated with transaction-level ESL tools and software debuggers, target hardware systems, as well as Verilog, SystemVerilog and VHDL simulators. EVE is a member of OCP-IP and ARM, Mentor Graphics, Real Intent, Springsoft and Synopsys Partner programs. Follow EVE on Twitter at www.twitter.com/EVETEAM and on Facebook at: tiny.cc/hykzr. Its United States headquarters is in San Jose, Calif. Telephone: (408) 457-3200. Facsimile: (408) 457-3299. Corporate headquarters is in Palaiseau, France. Telephone: (33) 1 64.53.27.30. Fax: (33) 1 64.53.27.40. Email: info@eve-team.com. Website: www.eve-team.com.

WHO: Forte Design Systems™, leading provider of software products that enable design at a higher level of abstraction and improve design results

WHAT: Will demonstrate the latest version of Cynthesizer™ SystemC high-level synthesis at DVCon 2012 in Booth #404

WHEN: Tuesday, February 28, from 3:30-6:30 p.m., and Wednesday, February 29, from 4:30-7 p.m.

WHERE: Doubletree Hotel, San Jose, Calif.

Thomas Tessier, vice president of Research and Development at Paneve LLC, will describe Paneve’s experiences using Cynthesizer with a paper, “Designing, Verifying, and Building an Advanced L2 Cache Subsystem Using SystemC” at DVCon. It will be presented during Session 3 titled SystemC and Beyond,” to be held Tuesday, February 28, from 9 a.m.-10:30 a.m.

For more details about Forte and Cynthesizer, go to: www.ForteDS.com.

Information on DVCon can be found at: www.dvcon.org.

About Forte Design Systems

Forte Design Systems is a leading provider of software products that enable design at a higher level of abstraction and improve design results. Its innovative synthesis technologies and intellectual property offerings allow design teams creating complex electronic chips and systems to reduce their overall design and verification time. More than half of the top 20 worldwide semiconductor companies use Forte’s products in production today for ASIC, SoC and FPGA design. Forte is headquartered in San Jose, Calif., with additional offices in England, Japan, Korea and the United States. For more information, visit www.ForteDS.com.

Verific Design Automation, supplier of industry-standard, IEEE-compliant SystemVerilog and VHDL front-end solutions, has been selected by Blue Pearl Software to support its Blue Pearl Software Suite.

The Blue Pearl Software Suite is register transfer level (RTL) analysis software used by field programmable gate array (FPGA) and application specific integrated circuit (ASIC) designers. Verific’s SystemVerilog and VHDL parsers and RTL elaborator have been integrated with Blue Pearl’s leading-edge software used for comprehensive RTL analysis, clock-domain crossing checks (CDCs) and automatic Synopsys Design Constraints (SDC) constraint generation. This announcement corresponds to Blue Pearl Software’s introduction today of version 6.0 of its software suite.

“It was logical to us to choose Verific Design Automation for the 6.0 version of the Blue Pearl Software Suite since Verific is an instantly recognizable brand-name provider of Verilog, SystemVerilog and VHDL parsers,” remarks Scott Aron Bloom, Blue Pearl’s director of product development. “Design teams applauded us when we selected Verific as the front-end for our Blue Pearl Software Suite.”

“Blue Pearl Software wisely determined that building and supporting in-house parsers for Verilog, SystemVerilog and VHDL is simply not cost-effective and can be counterproductive,” affirms Michiel Ligthart, Verific’s chief operating officer. “Blue Pearl’s differentiator is its ability to create and verify timing constraints and that is what its development team is focusing on. This is a sound decision and the correct one for Blue Pearl customers.”

The Blue Pearl Software Suite automates design analysis, CDC checking and Synopsys Design Constraints (SDC) creation, visualization and validation, giving users immediate feedback through powerful visualization techniques for validating automatically generated timing constraints.

Since its founding in 1999, Verific’s software has served as the front end to a wide range of EDA and FPGA tools for analysis, simulation, verification, synthesis, emulation and test of register transfer level (RTL) designs. Additionally, Verific recently announced availability of its UPF parser, now part of the Verific Parser Platform. Verific’s software is distributed as C++ source code and compiles on all 32- and 64-bit Unix, Linux and Windows operating systems.

About Blue Pearl Software

Blue Pearl Software, Inc. provides next-generation electronic design automation (EDA) software that uses new and innovative technology to reduce design flow iterations and increase designer productivity early in the digital design flow. The Blue Pearl Software Suite checks register transfer level (RTL) designs for functional errors and automatically generates comprehensive and accurate Synopsys Design Constraints (SDC) that improve quality of results (QoR) and reduce FPGA and ASIC design risks.

Visit Blue Pearl Software at www.bluepearlsoftware.com.

About Verific Design Automation

Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides de facto standard front-end solutions supporting SystemVerilog, Verilog and VHDL design. Verific’s software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: info@verific.com. Website: www.verific.com.

SANTA CLARA, Calif., Feb. 8, 2012 — IBM (NYSE: IBM), Samsung Electronics, Co., Ltd., and GLOBALFOUNDRIES — forming the world’s largest chip-making consortium — will preview the future of silicon technology at the 2012 Common Platform Technology Forum to be held at the Santa Clara Convention Center on March 14.

The companies will address next-generation semiconductor innovation covering critical topics such as 28-, 20- and 14-nanometer processes, as well as innovations beyond 14nm and 450mm wafer manufacturing. Technology jointly developed by the Common Platform companies — including more than 20 additional member companies — power the majority of the world’s mobile devices and consumer electronics.

Registration for the complimentary, one-day event at the Santa Clara Convention Center opens today. To register visit www.meetingconsultants.com/CommonPlatform/IBMBL[...]

“The Common Platform alliance is built upon an unmatched legacy of invention and deep commitment to research and development from IBM. The expertise of the companies is driving breakthrough technology innovations for semiconductor manufacturing. Our extensive and open ecosystem, focused on core manufacturing capabilities, gives our customers a flexible way to bring a wide range of semiconductor products to market,” said Michael Cadigan, general manager of IBM’s microelectronics division.

The Common Platform Technology Forum will include keynotes from industry leaders and presentations from senior members of the Common Platform partners’ management and technical teams. The forum will focus on collaboration for technology delivery, highlighting the rich and broad ecosystem of design enablement and implementation partners through a Partner Pavilion featuring leading EDA, IP, library, mask, packaging and design services companies.

About the Common Platform

IBM, Samsung, GLOBALFOUNDRIES and more than 20 additional companies form the Common Platform alliance; focusing on leading-edge, jointly developed digital CMOS process technologies and advanced manufacturing. The Common Platform model is supported by a comprehensive ecosystem of design enablement and implementation partners from the EDA, IP and design services industries. This ecosystem allows foundry customers to source their chip designs to multiple 300mm foundries with minimal design work, unprecedented flexibility and choice.

Breker Verification Systems, The SoC Verification Company, today announced that it closed calendar year 2011 with year-over-year growth of more than 150%, confirming its position as the first electronic design automation (EDA) company to solve the functional verification challenges of complex system-on-chip (SoC) designs containing embedded processors.

Additionally, Breker recently relocated its corporate headquarters from Austin, Texas, to Fremont, Calif., and added noted EDA entrepreneur and verification expert Michel Courtoy to its board of directors. TrekSoC™, the first commercially available software that automates the generation of self-verifying test cases for multi-threaded SoC devices, is in production use at leading semiconductor companies in the U.S., Europe, and India. The latest version of TrekSoC will begin shipping in late February. More details will be available then.

“2011 was a momentous year for Breker,” remarks Adnan Hamid, Breker Verification Systems’ co-founder and chief executive officer (CEO). “We made some strategic changes to position for rapid growth and firmly establish ourselves as The SoC Verification Company. From all calculations, these moves are paying off handsomely.” For example, Breker saw year-over-year sales growth of 150% and tripled the number of licenses in active use.

Since its founding in 2003, Breker Verifications Systems’ mission has been to improve upon existing verification technologies, especially as more and more chips become SoCs with embedded processors. Effective verification of such designs requires high-quality, self-verifying test cases running on the processors. These test cases must exercise a wide range of functional scenarios to ensure that the SoC can support the necessary concurrency, system-level and software functionality while meeting performance requirements. TrekSoC can generate these test cases automatically.

“It’s rare to work with entrepreneurs with a focused and clear idea of where the company’s going and how it’s going to get there,” says Board Member Michel Courtoy. “Breker has a long-term strategic vision that’s both impressive and sound, and a team that can implement the vision.”

About Board Member Michel Courtoy

Courtoy began his career at Intel in design engineering and software engineering. He managed product marketing for layout verification software at Cadence Design Systems. As vice president of marketing for Silicon Perspective, Courtoy created the market for silicon virtual prototyping and was a key player in its acquisition by Cadence in 2001. He served as a vice president at Cadence before becoming the CEO at Certess, leading Certess through sales growth to a successful exit by acquisition. Courtoy holds a Bachelor of Science degree in electrical engineering from University Catholique de Louvain, Belgium; a Master of Science degree in Electrical Engineering from University of California, San Diego; and an MBA from Santa Clara University in Santa Clara, Calif.

About Breker Verification Systems

Breker Verification Systems is an Electronic Design Automation (EDA) software company that provides innovative solutions to solve the challenge of complex system-on-chip (SoC) functional verification. Its TrekSoC™ software and unique SoC scenario-modeling™ approach are used in production at leading semiconductor companies in the U.S., Europe and India. Founded in 2003, it is privately held and funded, and based in Silicon Valley, Calif. Breker Verification Systems corporate headquarters are located at 304 Anza St., Fremont, Calif. 94539. Telephone: (512) 415-1199. Email: info@brekersystems.com. Website: www.brekersystems.com.

WHO:

EVE, the leader in hardware/software co-verification

WHAT:

Will exhibit at SemIsrael Verification Day, the largest and most focused event for the Silicon Verification sector

When:

Tuesday, February 14, from 8:45 a.m.-3 p.m.

Where:

Green House, Tel Aviv, Israel

SemIsrael attendees will have an opportunity to learn about EVE’s new ZeBu-Blade2 hardware-assisted verification platform, the first member of the ZeBu emulation family based on Xilinx Virtex6-LX760 field programmable gate arrays (FPGAs). The desktop emulator supports full-chip application specific integrated circuit (ASIC) and system-on-chip (SoC) designs of up to 32-million ASIC gates, and offers fast execution and attractive pricing for best-in-class hardware/software integration ahead of silicon availability.

For more information on EVE and its hardware/software co-verification platforms, visit: www.eve-team.com.

The SemIsrael Verification Day website can be found at: www.semisrael.com/component/option,com_fabrik/Itemid,240/fabrik,12/random,0/view,form/

About EVE

EVE is the worldwide leader in hardware/software co-verification solutions, offering fast transaction-based co-emulation and in-circuit emulation, with installations at five of the top six semiconductor companies. EVE products shorten the overall verification cycle of complex integrated circuits and electronic systems designs. Its products can be integrated with transaction-level ESL tools and software debuggers, target hardware systems, as well as Verilog, SystemVerilog and VHDL simulators. EVE is a member of OCP-IP and ARM, Mentor Graphics, Real Intent, SpringSoft and Synopsys Partner programs. Follow EVE on Twitter at www.twitter.com/EVETEAM and on Facebook at: tiny.cc/hykzr. Its United States headquarters is in San Jose, Calif. Telephone: (408) 457-3200. Facsimile: (408) 457-3299. Corporate headquarters is in Palaiseau, France. Telephone: (33) 1 64.53.27.30. Fax: (33) 1 64.53.27.40. Email: info@eve-team.com. Website: www.eve-team.com.

Verific Design Automation, supplier of industry-standard, IEEE-compliant SystemVerilog and VHDL front-end solutions, today announced immediate availability of a parser for the IEEE 1801-2009 Standard for Design and Verification of Low-Power Integrated Circuits.

Also known as Unified Power Format 2.0 (UPF 2.0), it was developed by standards organization Accellera and carries the support of multiple electronic design automation (EDA) vendors.

“We are happy to announce that we are having a fruitful collaboration with Verific on the UPF support of our products,” remarks Chouki Aktouf, CEO at DeFacTo Technologies. “As we expected from previous collaborative experiences with Verific, our R&D team is having real positive interactions and getting outstanding support from Verific’s R&D team.”

Since its founding in 1999, Verific’s software has served as the front end to a wide range of EDA and FPGA tools for analysis, simulation, verification, synthesis, emulation and test of register transfer level (RTL) designs. The UPF parser is part of Verific’s Parser Platform and is available standalone or as an add-on to existing SystemVerilog and VHDL installations. As with all Verific’s products, it is licensed as C++ source code.

About Verific Design Automation

Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides de facto standard front-end solutions supporting SystemVerilog, Verilog and VHDL design. Verific’s software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: info@verific.com. Website: www.verific.com.

Carbon Design Systems™, the leading supplier of virtual platform and secure model solutions, today announced immediate availability of virtual reference platforms on its Carbon IP Exchange Web Portal, found at www.carbonipexchange.com.

“Carbon’s virtual reference platforms have been used successfully by multiple designers to quickly get up and running,” remarks Bill Neifert, chief technology officer at Carbon.

Available for many of the most popular virtual models, including the ARM® Cortex™ A15, ARM Cortex A9, ARM Cortex R4 and MIPS® 34Kc, they contain models, software and configuration information to enable a designer to be productive in minutes. Some designers use these platforms for debugging firmware and for doing performance optimization within minutes. Others use a virtual reference platform as a starting point to eliminate the traditional learning curve associated with using new intellectual property (IP).

Processor models are combined with peripheral models, such as the ARM PL301 and ARM PL190, to form a reference implementation used as a starting point for further platform creation or as a standalone design environment. Software is included with each platform to configure the processor and peripherals and to execute a sample program.

Availability

Carbon virtual reference platforms are available today for ARM Cortex A15, ARM Cortex A9, ARM Cortex A8, ARM Cortex R4, ARM Cortex M4, ARM Cortex M3, ARM Cortex M0, ARM 1176, ARM 1136, ARM 968, ARM 946, ARM 926, ARM 7TDMIS, MIPS 34Kc, MIPS M14Kc and MIPS M14K. Additional reference platforms are being added regularly.

For the complete list, visit Carbon IP Exchange, found at: www.carbonipexchange.com. Carbon virtual reference platforms are available to Carbon SoCDesigner Plus users at no charge.

About Carbon Design Systems

Carbon offers the industry’s only unified virtual platform solution along with the leading solution for accurate IP model creation. Carbon virtual platforms can execute at 100s of MIPS and with 100% accuracy to enable application software development, detailed architectural analysis and secure IP model distribution. Carbon’s solutions are based on open industry standards, including SystemC, IP-XACT, Verilog, VHDL, OSCI TLM, MDI, CASI, CADI and CAPI. Carbon’s customers are systems, semiconductor, and IP companies that focus on wireless, networking, and consumer electronics. Carbon is headquartered at 125 Nagog Park, Acton, Mass., 01720. Telephone: (978) 264-7300. Facsimile: (978) 264-9990. Email: info@carbondesignsystems.com. Website: www.carbondesignsystems.com.

Mentor Graphics Corporation today announced that it has acquired the Flowmaster Group, a global leader in 1D Computational Fluid Dynamics (CFD) simulation software for system design. 1D CFD solutions allow for very rapid engineering design of complex fluid flow network systems like water-cooled electronic racks, automotive vehicle thermal management, and aerospace fuel systems. This acquisition consolidates the position of Mentor Graphics as the first EDA company to move into the adjacent Computer-Aided Engineering (CAE) mechanical analysis space.

The Flowmaster Group is a Dutch owned, UK-based international organization with over twenty years experience providing industry-leading, thermo-fluid systems simulation software to the aerospace, automotive, marine, oil and gas, power generation, process, rail and water industries. Flowmaster software is used by a wide range of engineering professionals to improve complex internal fluid systems from conceptual idea to finalized design. Flowmaster provides users with greater systems insight and foresight upfront of system development cycles significantly reducing the overall timescales involved.

The acquisition of Flowmaster complements the acquisition of Flomerics Limited by Mentor Graphics in 2008, the leading player in the general purpose, 3D multi-CAD embedded CFD and 3D electronics cooling thermal analysis sectors, and broadens the Mentor Graphics portfolio in the CFD space. The combination of the CFD software products and services from Mentor Graphics and Flowmaster, both targeted at engineers, designers and analysts, is expected to provide the most comprehensive set of upfront and concurrent CFD design tools available in the market today. The terms of the transaction were not disclosed.

We are very excited about the technical expertise and industry leading solutions that Flowmaster adds to our mechanical analysis simulation capabilities, said Erich Buergel, general Manager, Mechanical Analysis Division, Mentor Graphics. Both companies have world-class products in their respective sectors, a loyal set of customers and employees, and share a passion for pioneering fast design tools for engineers. This unique combination of solutions will allow us to meet the reliability, cost efficiencies, and time-to-market pressures of our respective user bases throughout the world, enhancing the quest for real-time engineering design solutions for a wide range of industries. We are impressed by the strong customer base and the existing relationships. We recognize the importance of a strong stable foundation which will be the platform for future innovations.”

The acquisition by Mentor Graphics brings together two companies with market-leading pedigrees and a shared vision for design tools to provide the unique goal of real-time, 1D-3D CFD solutions and decision making” said Alan Berry, CEO of the Flowmaster Group. Our two R&D teams and complementary industry strengths will accelerate our ability to deliver innovative simulation software technologies to our customers, thereby enhancing their product design and as a result their competitive advantage.

Aldec, Inc., in collaboration with SynthWorks Design Inc., today announces the availability of Open Source – VHDL Verification Methodology (OS-VVM™), underscoring the partnership’s commitment to provide continued support to the VHDL design community.

OS-VVM delivers advanced verification test methodologies, including Constrained and Coverage-driven Randomization, as well as Functional Coverage, and provides advanced features to engineers designing ASICS and FPGA-based applications using VHDL.

Igor Tsapenko, Aldec Director of Engineering, comments: “Hardware description languages such as VHDL and Verilog have provided electronics design engineers the ability to create complex digital projects. However, the challenge that many designers face is how to support system-level design requirements. In recent years, new language standards such as SystemVerilog and SystemC have emerged to aid in performing advanced system verification tasks, leaving VHDL designers with the dilemma of learning a new language.”

Jim Lewis, Director of VHDL Training at SynthWorks, adds: “The unique feature of OS-VVM is the ability to use live results of Functional Coverage to control randomization of stimulus. This ‘intelligent coverage’ helps minimize the number of test cases that need to be generated to achieve complete coverage – resulting in fewer simulation cycles and a higher velocity of verification.”

The benefits of OS-VVM include:

- It provides access to advanced randomization and functional coverage capabilities (previously available only within system-level methodologies) that can be used in any testbench; 

- Rather than using a constraint solver, balance in the randomization is achieved by interacting with the functional coverage model, resulting in fewer cycles; 

- The initial randomization is refined by using procedural code which can easily mix directed, algorithmic, file based methods and additional randomization; and 

- Straightforward usage model, ensuring users are able to get up to speed quickly while retaining the freedom and flexibility to continue using their HDL of choice. 

The latest versions of Aldec’s Active-HDL and Riviera-PRO EDA tools offer the advanced randomization and functional coverage capabilities provided by OS-VVM within the Options menu for VHDL-2008; i.e. no additional licenses are required.

SynthWorks, the maintainer of the OS-VVM packages, also offers in-depth training for OS-VVM and supplements with additional packages for creating scoreboards, memories, and abstracting interfaces.

Wokingham, UK – 4th January 2012. EnSilica, a leading independent provider of IC design services and system solutions, has opened a new design centre in India (Bangalore), to complement its existing design facilities in the UK. The new design centre will be a centre of excellence for the advanced verification of complex semiconductor products and IP. Verification services will be provided for both European and local customers based on a range of methodologies but with a particular focus on UVM (the Unified Verification Methodology) and SystemVerilog.

The new design centre will also provide a scalable resource for projects requiring larger teams to accelerate timescales or deal with complex tasks as well as broaden EnSilica’s design capabilities with the addition of new Verilog AMS (analog/mixed-signal) modelling, physical implementation and embedded software services. The new design centre will also further extend EnSilica’s existing turnkey ASIC and FPGA design capabilities with additional resources for developing EnSilica’s own portfolio of IP including its eSi-RISC highly configurable 16/32 bit embedded processors, eSi-Comms range of communications IP and eSi-Crypto encryption IP.

The Bangalore design centre will be headed by Ranganath Kempanahally as Director of Engineering. Ranganath has 15 years of wide ranging experience in ASIC design and verification roles in India, the USA and the UK. His broad spectrum of experience includes architecting advanced verification environments using eRM, OVM and UVM methodologies. He has a Masters in Electronics from the University of Mangalore, India and an MBA in “Finance and Entrepreneurship” from Cranfield School of Management in the UK.

EnSilica is actively seeking to recruit 30 skilled verification specialists for the new design centre in 2012. Applicants will be required to demonstrate experience in creating effective and pragmatic verification strategies, architecting the test environment and driving the verification process to a successful, on-time and on-budget conclusion.

“The opening of our new design centre in Bangalore, India, initially as a verification centre of excellence, is a strategic step in the ongoing development of our semiconductor services business,” said Ian Lankshear, CEO of EnSilica. “The new centre will provide a highly competitive, additional platform for our customers as well as a firm foundation for the development of a range of new and improved capabilities.”

About EnSilica

EnSilica is an established company with many years experience providing high quality IC design services to customers undertaking FPGA and ASIC designs. EnSilica has an impressive record of success working across many market segments with particular expertise in multimedia and communications applications. Customers range from start-ups to blue-chip companies. EnSilica can provide the full range of IC design services, from System Level Design, RTL coding and Verification through to either a FPGA device or the physical design for ASIC designs. EnSilica also offers a portfolio of IP, including a highly configurable 16/32 bit embedded processor called eSi-RISC, the eSi-Comms range of communications IP and eSi-Crypto encryption IP. For further information about EnSilica, visit www.ensilica.com.