ANDOVER, Mass.--Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced the MIPI-Xactor verification solution supporting the MIPI UniPro and M-PHY, and JEDEC UFS specifications.

MIPI-Xactor is a complete verification solution consisting of SystemVerilog UVM/OVM/VMM compliant Bus Functional Models (BFM), protocol checkers, directed and random compliance test suites, and reference verification frameworks. The MIPI-Xactor allows design and verification engineers to quickly and extensively test the functionality of UFS and UniPro/M-PHY compliant host and device controller-based designs.

“MIPI-Xactor builds on our solid foundation as a leading supplier of PCI Express and USB verification solutions to IP vendors and semiconductor companies,” said Chris Browy, vice president of sales and marketing of Avery Design Systems. “Our solution enables designers to thoroughly verify their designs functionally adhere to the new UFS and UniPro standards and effectively pinpoint areas of non-compliance or performance bottlenecks.”

Key Features

UFS Host

Emulates host driver and host controller

Supports command sets

- Native UFS

- SCSI SPC-4, SBC-3, SAM-5

UniPro Core

Emulates UniPro protocol stack layers and M-PHY

Supports all service primitives (SAP) and service data units (x_SDU)

DME User supports all sequences of control, configuration, and status primitives

- Allocates connections between CPorts

- Schedules message transfers between CPort Users

Supports CPort signal interface

Supports UniPro Test Feature

M-phy

LS-MODE and HS_MODE

LS-MODE NRZ and PWM signalling schemes

Multiple power saving modes

Layered environment based on family of SystemVerilog classes and methods

Abstract data model for transfer, packet, and descriptor types

Drivers, event callbacks, and scoreboard options automate status and result checking

Robust error injection enables modifying, adding, or deleting frames

UFS and UniPro transaction trackers (command and packet exchanges)

Random scenario generation with constraints stress design operation

Functional coverage monitoring of scenario cases

VMM/UVM/OVM support

Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for automatic property and coverage generation, X verification, and RT-level DFT at-speed testability analysis; robust core-through-chip-level Verification IP for PCI Express, USB, AMBA, and MIPI standards; and scalable distributed parallel logic simulation. The company is a member of the Synopsys SystemVerilog and VMM Catalyst Programs, Mentor Graphics Modelsim Value Added Partnership (VAP) program, and has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.