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  • Cliosoft, Inc.  (1)
    • SOS Design Data and IP Management
      ClioSoft's SOS Design Data Collaboration Platform is built from the ground up to handle the requirements of hardware design teams. The SOS platform enables global team collaboration, design & IP reuse, and efficient management of design data from concept through tape-out. (+)

      Features:

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      • Version control integrated into design flow
      • Composite object support for cell views
      • Efficient multisite collaboration
  • ArchPro Design Automation  (1)
    • ArchPro MVSIM
      World's first Electronic Design Automation (EDA) solution for verification of Power Managed Designs (+)

      Features:

      • Supports ARM® Intelligent Energy Manager (IEM) technology
      • MVSIM enables the user to bring any system level architectural decision on voltage scaling into the Register Transfer Level (RTL) and verify it.
      • MVSIM works with mainstream simulators like ModelSim (Mentor Graphics Corp.), NC-Sim (Cadence Design Systems, Inc.) and VCS (Synopsys, Inc.) to verify multiple voltages.
  • ALDEC, Inc  (5)
    • Riviera-PRO
      Riviera-PRO is a common-kernel, mixed language, multi-platform simulator for Verilog, SystemVerilog, VHDL, SystemC/C/C++, Assertions and EDIF (+)

      Features:

      • It supports System Level Verification
      • Languages Supported: VHDL, Verilog HDL, SystemVerilog IEEE 1800 Design, SystemVerilog IEEE 1800 (Verification), SystemC TM 2.2 IEEE 1666/OSCI 2.2, Mixed language & EDIF 200V
      • Supported Platforms: Linux 32-bit, Linux 64-bit, Microsoft Windows, 2000/2003/XP/VISTA
    • HES
      HES (Hardware Emulation System) may be used for emulation, acceleration and prototyping (+)

      Features:

      • Emulation up to 10 MHz
      • Acceleration up to 500 KHz
      • Prototyping
    • ALINT
      ALINT™ is a VHDL and Verilog Design Rule Checking Tool used to analyze HDL source code against a comprehensive set of ASIC design guidelines for early bug detection, cross-probing (+)

      Features:

      • VHDL IEEE 1076 (1987, 1993, 2002 and 2008), Verilog (1995, 2001, 2005) and Mixed Language Design analysis/rule checking
      • STARC® VHDL Rule Library
      • STARC® Verilog Rule Library
    • Active-HDL 8.1 EE
      Active-HDL is a powerful mixed-language simulator with tools for graphical design entry, project management, HDL verification and documentation (+)

      Features:

      • A multi-vendor flow manager control
      • Languages supported: VHDL, Verilog® , SystemVerilog IEEE 1800 Design, SystemC TM 2.2 , Mixed language & EDIF 200V
      • Supported Platforms: Microsoft Windows 2000/2003/XP/VISTA
    • Riviera-IPT
      A high-speed co-verification and debug environment for complex embedded software/hardware co-development utilizing ARM processors (+)

      Features:

      • Based on Aldec+IBk-s VHDL and Verilog mixed-language simulation technology, Design Verification Manager, and a hardware accelerator with capacity up to 12 million gates
      • Riviera-IPT+IBk-s hardware accelerator allows designs to run at MHz speeds
      • Supports IEEE VHDL 1076-87/93, VITAL 2000, and Verilog 1364-2001 [...]
  • Calypto Design Systems  (2)
    • ESL HW Design and RTL Power Optimization
      Calypto Design Systems leads the industry in technologies for ESL hardware design and RTL power optimization. These technologies empower designers to create high quality and low power electronic systems for today’s most innovative electronic products. (+)

      Features:

      • Catapult lets designers use industry standard ANSI C++ or SystemC to describe functional intent at the ESL level. From these high-level descriptions, Catapult automatically generates production quality RTL to dramatically shorten both design and verification in today’s hardware design flows.
      • PowerPro is an automated RTL power optimization and analysis product that identifies and inserts sequential clock gating and memory enable logic into synthesizable Verilog and VHDL designs. PowerPro has proven to reduce power by up to 60% in RTL designs.
      • SLEC is a sequential equivalence checker that handles differences in design state, timing and levels of abstraction. SLEC enables ESL hardware design by using formal methods to comprehensively proving equivalence between RTL implementations and system-level models. [...]
    • Calypto PowerPro MG
      Makes memory gating logic that works hand in hand with memory modes like light sleep, deep sleep, and shutdown in Virage Logics's SiWare memory compilers (+)

      Features:

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      • The memory compiler automatically generates a PowerPro MG Model, which STARC has implemented in a seamless, low-power EDA design flow
      • The collaborating companies claim 50 percent dynamic power reduction and 40 percent leakage power reduction with the approach, which is outstanding news for SoC designers [...]
  • GLOBALFOUNDRIES  (1)
    • GLOBALFOUNDRIES Services
      GLOBALFOUNDRIES, one of the world's top three dedicated silicon foundries, is forging a customized approach to outsourced semiconductor manufacturing by building lasting and collaborative partnerships with its customers. GLOBALFOUNDRIES' focus on enabling system-level technologies facilitates the convergence of communications, computing and consumer electronics. We operate with our customers' overall objectives in mind by providing complete solutions enabling them to deliver better, faster and cheaper products to market. Technology expertise is key to success in our industry. At GLOBALFOUNDRIES we are helping to accelerate the technology convergence taking place in the electronics industry, by anticipating the changing needs for our customers. Whether our customers are integrated device manufacturers, fabless, or system companies, they need the fundamental building blocks in silicon to address the cost-effective system solutions that today's and tomorrow's convergence applications require. The design of today's complex integrated circuits requires state-of-the-art electronic design automation (EDA) software tools, design intellectual property (IP), and design services. GLOBALFOUNDRIES supports customers in achieving successful designs by partnering with leading providers in the EDA, IP, and design services areas. This enables our customers to integrate system-level functionality in their products with accelerated time to market along with reduced design and manufacturing risks. We work with our partners very closely on technical and business aspects, providing our customers an advantage of having the best technical solutions available in a seamless fashion. GLOBALFOUNDRIES has an active alliance program to validate our partners' EDA tools, libraries and design IP with our silicon process technologies to insure that they meet the highest standards. FEATURES: DDR I/O (DDRI/II) General Purpose I/O (Inline / Staggered) Register File Memory Compilers Specialty I/O (HSTL, SSTL) SRAM Memory Compilers Standard Cell Libraries [...] (+)

      Features:

  • National Semiconductor  (2)
    • NSC Ref Designs
      Six new reference designs from National Semiconductor Corp. enable products that consume less power, extend battery life and generate less heat (+)

      Features:

      • PowerWise reference designs combine energy-efficient devices and arrange them in a system to actively lower power consumption and reduce heat dissipation
      • Each proven PowerWise reference file kit includes applicable design schematic, bill of materials (BOM), board layout, firmware, design documentation and field-programmable gate array (FPGA) source code in synthesizable Verilog or VHDL
      • The designs address a wide range of applications including portable, lighting, solar, industrial, medical, communications infrastructure, and test and measurement. For more information on these reference designs, visit www.national.com/refdesign
    • SP16160CH1RB
      Intermediate frequency (IF) sampling receiver reference design for multi-carrier, multi-standard wireless basestations addressing GSM/EDGE, WCDMA, LTE and WiMAX standards (+)

      Features:

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      • The SP16160CH1RB operates from a single 5V supply and includes the dual-channel ADC16DV160 16-bit, 160 mega-samples per second (MSPS) pipeline ADC, dual-channel LMH6517 DVGA, and LMK04031B clock jitter cleaner
      • The overall performance of the reference design is enabled by the high dynamic performance of the ADC, the low-noise and high-linearity of the DVGA and ultra-low rms jitter of the clock jitter cleaner. The ADC16DV160 delivers a signal-to-noise ratio (SNR) of 76.3 dBFS and SFDR of 91.2 dBFS at 192 MHz input IF, while the LMH6517 provides a noise figure of 6 dB and OIP3 of 45 dBm, and the LMK04031B clock jitter cleaner offers near 150 fsec of rms clock jitter
      • The SP16160CH1RB delivers an IF chain receiver sensitivity of -105 dBm, with a 9 dB carrier-to-noise ratio in a 200 kHz channel, at 192 MHz input IF
  • Synopsys, Inc.  (4)
    • Synplify Premier
      The Synopsys FPGA design solution comprises high-quality, high-performance, and easy-to-use FPGA implementation and debug tools (+)

      Features:

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      • Designers using the Synopsys FPGA design tools gain fast time-to-results for complex FPGAs, area optimization for cost and power reduction, multi-FPGA vendor support, and incremental and team-design capabilities for faster FPGA design development
      • The Synopsys FPGA design tools also provide additional value by offering DesignWare IP integration, links to high-performance functional verification with VCS, integration with Synphony Model Compiler, and an ASIC compatible synthesis flow for FPGA-based prototyping
      • As part of the Synopsys FPGA Design Solution, Synplify Premier software performs FPGA synthesis for programmable devices sold by Actel, Achronix, Altera, Lattice Semiconductor, Silicon Blue and Xilinx
    • SPW Hardware Design System (HDS)
      Fastest path from innovation into implementation for digital signal processing systems, applying a model-based design approach (+)

      Features:

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      • At its core is the C Data Flow (CDF) modeling paradigm, which enables the most efficient description of digital signal processing systems which may be implemented in dedicated digital hardware or embedded software
      • SPW Hardware Design System (HDS) is a key component in the SPW product family
      • It accelerates the hardware design, verification, and analysis of complex, algorithm intensive Digital Signal Processing (DSP) systems
    • Synplify Premier
      Graph-based Physical Synthesis; fast timing closure and a push-button performance boost of up to 20 percent (+)

      Features:

      • RTL-based Verification Technology; offers the fastest method of finding functional errors in a design thanks to simulator-like visibility into a live, running FPGA with real-world stimulus
      • Automatic Handling of DSP functions; infers DSP functions from RTL and maps into vendor's DSP hardware (such as MAC)
      • ASIC design-style support; built-in gated clock conversion and a DesignWare compatible library enables ASIC code to be implemented into an FPGA without modification
    • IC Compiler 2010.03
      Physical implementation solution delivering up to 2.5X faster performance on multicorner/multimode (MCMM) designs, and enhanced In-Design technology for faster design closure (+)

      Features:

      • IC Compiler 2010.03 offers performance improvements across the board
      • It provides 2X faster time to initial floorplan creation and on-demand loading, which offers 2X to 3X faster time to final floorplan creation [...]
  • SystemCrafter  (2)
    • SC V2.00
      Design, debug, and simulate hardware and systems using existing C++ development environment (+)

      Features:

      • Synthesizes SystemC into RTL VHDL for Xilinx FPGAs
      • Integrated GUI for file management
      • Descriptions are fast to write, fast to simulate, maintainable, and readable
    • SystemCrafter SC v3
      SystemCrafter SC synthesises hardware designs written in SystemC to VHDL or Verilog (+)

      Features:

      • The HDL can be used with commonly available tools to target Xilinx FPGAs
      • Improved SystemC coverage, including support for state machines and combinatorial logic
      • New Verilog output
  • Avnet Electronics Marketing  (3)
    • Xilinx Virtex-6 FPGA DSP Development Kit
      Geared toward military, wireless, instrumentation, and many other compute-intensive applications where high-performance DSP is a must (+)

      Features:

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      • The kit is part of the Xilinx Targeted Design Platform for DSP
      • The kit comprises Virtex-6 FPGAs, DSP IP, a scalable development board, cables, documentation, and DSP development tools
      • Virtex-6 DSP Targeted Reference Design, which conceptualizes DSP design flows and methodologies for Virtex-6
    • AdvancedTCA Reference Design Kit
      Xilinx 2VP50 or 2VP70 FPGA (+)

      Features:

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      • CompactFlash programming card
      • PICMG compatible board form factor
      • 128 MB DDR SDRAM
    • Xilinx AdvancedTCA Reference Design Kit
      Xilinx 2VP50 or 2VP70 FPGA (+)

      Features:

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      • CompactFlash programming card
      • PICMG compatible board form factor
      • 128 MB DDR SDRAM
  • ON Semiconductor  (3)
    • 0.18 micron (µm) CM
      The ONC18 process is an ideal platform for developing low power and highly integrated digital and mixed-signal application-specific integrated circuit (ASIC) devices for automotive, industrial and medical applications (+)

      Features:

      • The ONC18-based solutions will be manufactured at ON Semiconductor's 8-inch wafer fabrication facility in Gresham, Oregon, so the process is also expected to prove attractive for designers of U.S. military applications seeking domestic production with ITAR-compliant partners
      • ONC18 will allow designers in the automotive, industrial, medical and military sectors to develop integrated, low-power digital and mixed-signal ASICs quickly and cost-effectively
      • The ‘on-shore' nature of the fabrication will be particularly useful for US military customers, while planned developments for the process further underline ON Semiconductor's commitment to the custom foundry business
    • GreenPoint®
      GreenPoint Reference Designs for High Efficiency LED Lighting Applications (+)

      Features:

      • Reference designs simplify development of MR16 format products and LED-based ENERGY STAR residential luminaires
      • Configured in size and features for MR16 LED replacements, the first reference design describes a built and tested 3 watt (W) to 5 W LED driver solution for driving high-brightness LEDS (HB-LEDs). The second design is targeted at designers looking to achieve compliance with the ENERGY STAR® 1.1 requirements for Solid State Lighting (SSL) in residential luminaire applications and describes a built and tested off-line GreenPoint solution for an isolated 8 W constant current LED driver
      • Each of the new reference designs addresses all of the functional blocks needed to create a complete application and is available as a package that includes description, schematics, bill-of-materials (BoM), Gerber files and evaluation guidelines
    • ON Semiconductor Launches IPD2 Process Technology that Combines HighQ Performance and Small Size for Portable Electronics Applications (+)

      Features:

      • ON Semiconductor has introduced a new integrated passive device (IPD) process technology
      • An enhancement of the company's existing HighQ copper (Cu) on silicon (Si) IPD technology, the new IPD2 process features a second 5um copper layer that increases inductor performance, allows greater flexibility, and supports the design of highly precise, cost-effective IPDs for RF system in package applications in portable electronics equipment
      • One of a number of innovative manufacturing services offered by ON Semiconductor's custom Foundry Division, the HighQ IPD2 process utilizes advanced 8-inch wafer technology
  • SynaptiCAD, Inc.  (9)
    • BugHunter Pro
      Updated graphical test bench generator and HDL debugger, to add support for SystemC and C++ simulations (+)

      Features:

      • Standalone SystemC and mixed SystemC/Verilog/VHDL simulations
      • BugHunter shows cause-effect dependency windows that show relationships between signals and process statements in a Verilog simulation
      • Simplifies compiling regular C++ applications in conjunction with an HDL simulation
    • VeriLogger Extreme
      VeriLogger Extreme is a high-performance compiled-code Verilog 2001 simulator that offers fast simulation of both RTL and gate-level simulations with SDF timing information (+)

      Features:

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      • Comes with BugHunter Pro a graphical Verilog/VHDL integrated development environment
      • Supports source-level debugging, with breakpoints that are saved a the project level and are not lost after code changes
      • Waveform compression engine for high-speed waveform dumping
    • Gates-on-the-Fly
      Gates-on-the-Fly (GOF) graphically analyzes and edits large Verilog netlists that have been generated from a synthesis or layout tool (+)

      Features:

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      • GOF can edit Netlists that require changes to either meet timing closure specifications, fix functional logic bugs, or to repartition a design
      • Using GOF, you can easily find and view specific logic cones in your design on a schematic to visualize just the paths you need to see without unnecessary clutter
      • GOF also simplifies mapping from RTL level constructs to their gate-level equivalents, so that you can pinpoint the locations where changes need to be made
    • Verilogger Extreme
      VeriLogger Extreme is a completely new, high-performance compiled-code Verilog 2001 simulator that significantly reduces simulation debug time (+)

      Features:

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      • VeriLogger Extreme offers fast simulation of both RTL and gate-level simulations with SDF timing information
      • VeriLogger Extreme supports design libraries and design flows for all major ASIC and FPGA vendors, including Actel, Altera, Atmel, LSI Logic, QuickLogic, and Xilinx
      • BugHunter Pro graphical debugger included with purchase of VeriLogger Extreme [...]
    • TestBencher Pro
      Generates reactive VHDL, Verilog, and SystemC test benches and bus-functional models from language-independent timing diagrams (+)

      Features:

      • Can apply different stimulus vectors depending on simulation response so that the test bench functions as a behavioral model of the environment in which the system being tested will operate
      • Suitable for testing large FPGA and ASIC designs [...]
    • BugHunter Pro
      BugHunter Pro is a debugging environment for VHDL and Verilog simulators that provides unit-level test bench generation, exceptional VCD support, and project management (+)

      Features:

      • The unit-level test bench generation is unique in that it lets the user draw stimulus waveforms and then generates the stimulus model and wrapper code and launches the code
      • It is one of the fastest ways to test a model and make sure that everything is working correctly
      • Waveform window displays both the simulation results and the stimulus waveforms for the test bench generation
    • Gates-on-the-Fly
      Gates-on-the-Fly (GOF) graphically analyzes and edits large Verilog netlists that have been generated from a synthesis or layout tool (+)

      Features:

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      • Locate Sections of interest in the design in GofViewer
      • View sections of the design as a schematic using a GofTrace incremental schematic window
      • GofECO is a graphical method of changing a netlist
    • Transaction Tracker
      Transaction Tracker is a PSL/Sugar-based verification tool for viewing simulation data as higher-level transactions, instead of as simple waveforms (+)

      Features:

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      • Transaction Tracker can read VHDL and Verilog simulation results, Agilent and Tektronix file formats, plus BTIM files (SynaptiCAD's 200x-compressed binary format)
      • SynaptiCAD's gigawave feature is included with Transaction Tracker stand-alone, allowing gigabyte-size files to be loaded into the tool
      • Equations are written in the PSL/Sugar language
    • WaveFormer Pro
      WaveFormer Pro combines a timing diagram editor, a stimulus generator, and an interactive HDL simulator (+)

      Features:

      • Automatically generate and simulate timing diagrams using common Boolean and registered logic equations
      • Import or export waveforms to VHDL, Verilog, HP's logic analyzers and pattern generators, SPICE, ABEL, and a variety of gate-level simulators
      • Download WaveFormer Pro from www.syncad.com [...]
  • Startech Global  (1)
    • ATCA R&D Services
      Startech Global specializes in offering product engineering services and systems solutions for AdvancedTCA, MicroTCA, and AdvancedMC design anddevelopment (+)

      Features:

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      • Board Design: Architecture, PCB design, power optimization, shelf management, high-level hardware synthesis
      • Prototype Development: PCB prototyping and testing, ATE, NDT, in-circuit testing/BIST, boundary scanning
      • FPGA Design: EDA; Xilinx, Altera chips; programming, pin assignment, board design & implementation, ATE
  • Upverter  (1)
    • Electronics Design, Accelerated
      Upverter is the easy-to-use EDA software that elite hardware engineers use to rapidly design next-generation electronics on any OS, from anywhere. (+)

      Features:

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      • Schematic Capture
      • PCB Layout
      • Parts library
  • IOxOS Technologies SA  (1)
    • TOSCA
      Multi-platform FPGA Design Kit for high-end applications development (+)

      Features:

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      • Hardware independent. VHDL source code available. PEV1100 VME 6U Evaluation Hardware Platform available
      • PCI Express-Centric Architecture
      • Transaction Layer Packet (TLP) data packets routed through configurable full mesh switches
  • Agilent Technologies  (6)
    • ADS software
      An EDA platform for microwave and RF circuit and system design (+)

      Features:

      • Offers complete design integration to designers of cellular and portable products
      • Verilog-AMS co-simulation for simulating end-to-end system behavior with analog and digital components
      • W-Element Model for including RLGC files in simulations
    • ISS co-simulation module
      A co-simulation plug-in tool that links Agilent's Advanced Design System (ADS) electronic design-automation software to Texas Instrument's Code Composer Studio development environment (+)

      Features:

      • ADS supports mixed-signal design and simulation of analog, RF, and DSP in a single, integrated design environment [...]
    • EDGE Design Library
      A design library for Agilent's Advanced Design System (ADS) electronic design automation software (+)

      Features:

      • Helps designers ensure compliance with both the upcoming enhanced data-rate global system for mobile communication evolution (EDGE) standard and IS-136 time division multiple access (TDMA) communication systems
      • Consists of a complete set of behavioral models for baseband and RF system and circuit design
      • Enables designers to develop, optimize, and validate their designs within the same integrated environment [...]
    • 81200
      A data generator/analyzer platform that provides a test package for the design and production of integrated circuits for digital and mixed-signal devices (+)

      Features:

      • Channel capacity ranges from a 2-channel, 200 Mbit/sec generator to a 120-channel, 660 Mbit/sec generator/analyzer platform
      • The circuit characterization package includes three primary elements that include Agilent E4874A characterization software components, Agilent E4839A test fixture, and BestLink/81200 Electronic Design Automation tool
      • The characterization software components allow engineers to design and automate most measurement tasks, such as the integration and control of other instruments like a power supply [...]
    • 89600 series VSA
      A vector signal analyzer that provides a tightly linked, software/hardware design environment (+)

      Features:

      • Facilitates faster and easier communication system designs from initial design simulation to final hardware prototype
      • 36 MHz bandwidth capacity for measuring RF signals up to 2.7 GHz
      • Available with a VXI-based front end using one or two baseband inputs and covering bandwidths to 40 MHz
    • GS-8300 Wireless LAN Manufacturing Test System
      An integrated, tailorable test solution designed for chipset and reference design 802.11a, b. and g manufacturers who are developing, manufacturing, or testing WLAN modules (+)

      Features:

      • System software and fixturing
      • Support including calibration, maintenance, and spare parts
      • Services including capacity transfer, optimization, installation, training, RF expertise, and consulting
  • Synplicity  (3)
    • Synplify Pro
      Achieves industry-leading QoR by incorporating several advanced optimization techniques including proprietary Behavior Extracting Synthesis Technology (+)

      Features:

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      • By extracting behavior such as Finite State Machines, multipliers, and memories from RTL code and starting synthesis at this level, the Synplify Pro product optimizes a design globally for improved performance and at the same time can run faster and handle larger designs
      • By selecting a switch, a designer can tell the tool to automatically move registers inside combinatorial logic in order to balance timing delay and improve circuit performance by as much as 20 percent
      • Retiming may be used on a global level or selectively
    • Synplify DSP
      Model and simulate algorithms quickly, and automatically create optimized RTL implementations for a wide range of target devices (+)

      Features:

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      • Automated RTL implementation
      • Automatically generates RTL and a verification test bench from a Simulink system-level specification
      • No hand-coding of any RTL is required
    • Identify RTL Debugger
      A software tool that enables users to probe and debug FPGA designs directly in the source RTL (+)

      Features:

      • Allows users to navigate designs graphically and mark signals directly in RTL as probes or sample triggers
      • After synthesis, users can view results in the RTL source code or in waveform
      • Design iterations rapidly completed using incremental place and route
  • Mentor Graphics Corporation  (0)
  • IPextreme  (1)
    • USB20Hub
      Compliant to Universal Serial Bus Specification, Revision 2.0 (+)

      Features:

      • USB-IF Certified: TID# 30000009
      • Windows Hardware Quality Lab (WHQL) compliant
      • Silicon-proven design used in production USB 2.0 hub chips from Cypress Semiconductor
  • Modelithics, Inc.  (1)
    • Modelithics COMPLETE v17.1 for NI AWRDE
      The Modelithics Library is an extensive collection of scalable and very accurate simulation models for use in various EDA tools for RF and microwave electronic design. This new release is formatted for NI AWRDE (Microwave Office) and includes many new models for commercially available electronic components, plus new model features. (+)

      Features:

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      • High accuracy RF and microwave simulation models
      • Substrate, pad, and part value scalable
      • Accurate parasitic simulation
  • picoChip Designs Ltd.  (1)
    • HSPA Femtocell Software Reference Design
      High-Speed Packet Access (HSPA) femtocell software reference design from Continuous Computing and picoChip to combat poor cell phone reception and spotty coverage (+)

      Features:

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      • A femto (10E-15) cell is basically a miniature cell phone tower/repeater/infrastructure station that drastically improves cell phone reception
      • Combining Continuous Computing's Trillium Femtocell protocol software with picoChip's PC8208 software and PC202 picoArray SoC, the reference design reduces project risk and complexity and improves time-to-market
      • Design works with 3G/4G protocols at HSPA data rates
  • AGP Micro Ltd  (1)
    • xState Developer
      An EDA tool for the design and implementation of state machines (+)

      Features:

      • State machines are implemented in C by the automatic ANSI C90 code generator
      • Graphical hierarchical state machine notation
      • State machine diagram analysis for common design mistakes
  • Solido Design Automation Inc.  (1)
    • Variation-Aware Custom IC Design Software
      Solido Variation Designer is a scalable and extensible platform, targeted specifically at helping designers achieve maximum yield with optimal performance with solutions in four key areas: memory design, standard cell design, low power I/O design and analog/RF design. (+)

      Features:

      • Analyzes in minutes the billions of Monte Carlo samples necessary to evaluate bit cells and sense amps, enabling effective yield/performance tradeoff analysis.
      • Enables designers to efficiently and automatically size standard cells across PVT and high-sigma statistical corners, on pre- or post-layout designs.
      • Provides efficient verification of I/O blocks across all the defined power states in combination with PVT corners and post-layout RC corners.
  • S3 Group  (1)
    • SoC and RF SoC ASIC Design Services
      S3 Group has delivered over 500 successful IC designs down to 40nm since it was founded in 1986 and is a recognised world leader in SoC design. For SoC designers and product managers, S3 Group delivers a turnkey specification-to-packaged-parts service leveraging a comprehensive portfolio of IP to deliver power-efficient single-chip systems. FEATURES: Proprietary NanoFlow SoC acceleration flow from RTL to gdsII SoC internal digital buliding block and verification IP SoC high performance Mixed-Signal IP including data-converters, PLLs & power management SoC proprietary RF block IP and complete transceiver interfaces Full capability from system architecture through physical design and post-silicon validation All disciplines including RF circuit design, Analog Mixed-Signal, Digital and Embedded SW Chip manufacturing and productization through S3 Group partners [...] (+)

      Features:

  • Endeavor Intertech Corporation  (1)
    • CoOperate HDL
      A tool that transforms the Precyse Palm DSP processor model into a co-simulating model (+)

      Features:

      • Can be incorporated into a hardware design to provide instant co-simulation, without adding another tool to the tool chain
      • Provides full synchronization between the Precyse model and the HDL simulator while supplying a high throughput communication pipeline between the two
      • Enables multiple instantiations of the model in a design
  • Altium Limited  (2)
    • Protel
      A complete board-level and FPGA-level design solution in a single application (+)

      Features:

      • Fully supports the design of FPGAs and their integration onto the PCB
      • Based on LiveDesign-enabled DXP platform to provide seamless integration with other Altium design systems
      • Hierarchical, multi-channel schematic editing environment
    • CircuitStudio
      A decdicated universal front-end engineering design tool for both board-level and programmable device design (+)

      Features:

      • Integrates: hierarchical, multi-channel schematic capture, VHDL coding and functional simulation, SPICE 3f5/XSpice simulation, pre-layout signal integrity analysis, and more than 68,000 components (16,000 include simulation models)
      • Comprehensive design error checking
      • Able to define critical PCB data such as board outline, design rules, and component placement
  • AutoESL Design Technologies, Inc.  (1)
    • AutoPilot FPGA: No-compromise High-level Synthesis
      Support for fixed-point and floating-point arithmetic in C, C++ and SystemC (+)

      Features:

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      • Highest quality of results: delivered performance 35x compared to TI DSP processor on an Optical flow (Video) application
      • Extensive architectural exploration and “what-if” analysis without changing the source
      • Flexible interface synthesis for internal and external interfaces such as memories, FIFOs, buses and interfaces such as AXI
  • Blue Pearl Software  (1)
    • Accelerates IP & FPGA Verification
      Blue Pearl Software Inc is an electronic design automation company offers a unique and powerful approach to improving the process of designing computer chips or integrated circuits. Blue Pearl provides high performance, innovative, automated tools to generate and validate critical timing and functional information early in the design cycle. The Blue Pearl Software Suite includes RTL design analysis - linting, clock domain crossing analysis and automatic timing constraint (SDC) generation, that accelerates IP and FPGA verification. Toll free 1855-848-6600 [...] (+)

      Features:

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  • Tuscany Design Automation  (1)
    • Tego
      Physical Design Software to Accelerate Structured Design (+)

      Features:

      • Deterministic design closure
      • With performance, power and area as primary objectives, another key value is that structured physical designs generally follow a systematic and predictable path to closure
      • Closure usually comes faster than by traditional techniques involving more trial-and-error
  • Axys Design Automation, Inc.  (1)
    • SuperSim C (CARMEL
      A cycle-accurate simulator for Infineon's Carmel DSP Core (+)

      Features:

      • Cycle-accurate and pin-accurate C model for simulation in cycle-based simulation environments
      • Delay back-annotation of all pins for use in event-driven simulation environments
      • Fully verified against the golden reference RTL model of Infineon on hardware test sequences
  • Tanner EDA  (1)
    • HiPer Simulation AMS
      HiPer Simulation AMS integrates Tanner EDA's industry-renowned full-custom analog front end design suite with Riviera PRO TE from Aldec. (+)

      Features:

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      • Tightly integrated best of breed products for high productivity and reliability
      • Scalable – well-suited to growing needs of "big A/little D" designs
      • Industry-leading price-performance
  • Tarek Verification Systems  (2)
    • Draco-VA
      Reusable building blocks to implement a unified verification environment at all abstracted design levels, e.g., ESL, RTL, FPGA prototyping, and real silicon (+)

      Features:

      • Object-oriented data and data structure control and management automates brand-new test creation without programming effort
      • Fastest test bench architecture with scalable and intelligent building blocks to generate layered and transaction-oriented stimulus
      • Automatic ASIC configuration and register/memory testing from the specification
    • PCIE-VR
      Supports all the PCI Express standards, 1.0a, 1.1, and the coming Gen2 (+)

      Features:

      • All PCIE designs, such as root complex, switches, end points, and bridges, are supported at both Register-Transfer Level (RTL) and Electronic System Level (ESL)
      • To integrate a PCIE design, PCIE-VR uses standard interfaces, such as serial, PIPE, 8/10b, and parallel
      • A compliance test suite that implements the PCIE compliance checklist from PCI-SIG is also included
  • Carbon Design Systems  (2)
    • VSP
      VSP enables early chip and system validation by allowing multiple levels of abstraction to be simulated together including C, SystemC, RTL, IP cores, transaction-level, and instruction-level models. (+)

      Features:

      • VSP models are derived from a chip's RTL specification and have the benefits of drop-in interoperability, high-performance, and hardware-accuracy.
      • VSP software opens new doors for ESL adoption by allowing customers to incorporate IP and legacy RTL into a system simulation early in their design cycle
      • Firmware and the underlying virtual hardware can be validated together before tape-out, rather than waiting for first silicon or spending months to develop an approximate behavioral model [...]
    • Carbon Library of Implementation Accurate Models of ARM IP
      Carbon Model Studio is a complete solution for the automatic generation, validation, and execution of hardware-accurate software models. Carbon Model Studio delivers value throughout the entire design lifecycle. In a modern SoC, as much as 80% of the design is existing IP, either re-used from previous projects or provided by a third party. Carbon Model Studio enables the user to leverage this IP, in all of its configurations, to jumpstart the creation of complete, accurate virtual platforms. It is important to be able to use your hardware models in your choice of system environments. Carbon Model Studio was architected from the ground up to support any system simulation platform. There’s no need to develop unique models for each platform. Carbon Model Studio provides direct integration into the following platform environments: Carbon Model Studio’s many platform integrations mean that you have the versatility to use Carbon Models in all of your development environments. Software engineers can focus on a “data-book� view of the device for programming. Architects have access to the buses, interfaces and transactions. Hardware engineers have full debugability and visibility into the RTL including waveform dumping. Because the model is common, all of your teams can work on solving problems, instead of porting issues across environments. FEATURES: Accurate architectural analysis Presilicon software integration Secure external model distribution Automatically compiles RTL into high-speed software models Straightforward GUI manages model creation and validation Easy configuration management for model variants SoC Designer CoWare Platform Architect OSCI SystemC [...] (+)

      Features:

  • XILINX, Inc.  (15 of 21)
    • Zynq UltraScale+ MPSoC
      Based on the Xilinx UltraScale MPSoC architecture, the Zynq UltraScale+ MPSoCs enable extensive system level differentiation, integration, and flexibility through hardware, software, and I/O programmability. (+)

      Features:

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      • Innovative ARM® + FPGA architecture for differentiation, analytics & control
      • Extensive OS, middleware, stacks, accelerators, and IP ecosystem
      • Multiple levels of hardware and software security
    • Xilinx ISE Design Suite 11
      Logic, system, embedded and DSP domain-specific solutions (+)

      Features:

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      • PlanAhead™ Design Analysis tool for optimizing performance
      • ChipScope™ Pro Analyzer and Serial IO Toolkit for real-time debug and verification
      • System Generator for DSP for developing high-performance DSP systems using MathWorks products
    • Virtex-6 FPGA DSP Kit
      Provides a platform for next generation products that include digital signal processing (DSP) which need to deliver more performance and flexibility with shorter development cycles and less cost and power (+)

      Features:

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      • Out-of-the-box development solution that quickly builds confidence in developing DSP applications on FPGAs
      • Includes a Xilinx ML605 development board including a Virtex-6 LX240T FPGA, design tools, IP, reference designs, and documentation
      • Supports both traditional RTL and high-level design methodologies and can easily extended to include additional high-level design flows and I/O daughter cards through third party partners and standardized integration [...]
    • Avnet Spartan-6 FPGA DSP Kit
      Xilinx FPGAs exceed the computing power of DSPs with their inherent parallelism and offer co-processing methods of performance acceleration for signal processing (+)

      Features:

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      • The Xilinx Spartan-6 FPGA DSP Kit integrates hardware, IP, software development tools and methodologies together into solutions that accelerate development for experienced users and simplify the adoption of FPGAs for new users
      • With the addition of targeted reference designs, these DSP platforms enable users to focus on creating their own unique differentiation from the very beginning of the product development process
      • This kit includes the Xilinx Spartan-6 LX150T board and allows users to quickly learn the different tool flows and design techniques involved in creating DSP centric designs with the Spartan-6 FPGA family
    • ISE Design Suite 13
      ISE Design Suite 13 maximizes productivity by leveraging open industry standards to accelerate design creation, verifi cation, implementation, and lower system power for design teams targeting Xilinx FPGAs and Extensible Processing Platforms (+)

      Features:

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      • Plug-and-Play IP: The new AMBA 4 AXI-4 interconnect protocol IP enables design teams to easily customize their system topology for either performance or area, resulting in optimal system bandwidth for interconnect and memory interfaces
      • Accelerated Verification: Leveraging Xilinx's large portfolio of development boards, kits, and Xilinx's ISE Simulator new hardware Co-Simulation, verification engineers can test implemented blocks of the design while leaving blocks under development in the simulator, accelerating overall verification by up to 100 times faster than native simulation
      • Design Analysis:PlanAhead accelerates time to production with an integrated front-to-back environment with design analysis at each phase of the design cycle – RTL development, IP integration, verification, synthesis, place, and route. The end result is rapid convergence on power consumption, resource utilization, and performance with fewer time-consuming design iterations
    • Xilinx ISE Design Suite 12
      ISE Design Suite 12 software unlocks greater design productivity with breakthrough technologies for power optimization and cost (+)

      Features:

      • The Design Suite enables the fastest time to design completion with Xilinx Targeted Design Platforms – available in four configurations aligned to user-preferred methodology logic, embedded, DSP, or system design
      • Xilinx Targeted Design Platforms provide embedded, DSP, and hardware designers with access to an array of devices supported by open standards, common design flows, IP, and runtime platforms
      • The ISE Design Suite offers domain-specific design environments and enables designers to meet power and performance goals with Xilinx CPLDs and FPGAs, including the new Virtex-6 and Spartan-6 families
    • Xilinx ISE Design Suite 11
      ISE Design Suite 11 Embedded Edition delivers base-level FPGA features and technologies, plus all the embedded tools and IP needed to achieve greater design productivity and breakthrough performance, power, and cost benefits with Xilinx embedded processing solutions (+)

      Features:

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      • Platform Studio Design Suite and the EDK: Integrated development environment with embedded processing tools and design generators, MicroBlaze soft core, IP, software libraries, and third-party interfaces
      • Software Developers Kit (SDK) as stand-alone configuration: Eclipse-based software development environment for feature-rich C/C++ code editing and compilation, source code version control, and seamless debug and profiling of embedded targets
      • System Generator integration with SDK: Enables algorithm developers to use only the software development environment for the embedded portion of their designs [...]
    • ISE Foundation 8.2i
      A programmable logic design solution (+)

      Features:

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      • Supports the Virtex-5 family
      • Xilinx Fmax technology provides a powerful design closure environment
      • An integrated timing closure environment helps identify bottlenecks in Virtex-5 FPGA designs quickly and easily
    • Avnet Virtex-6 FPGA DSP Kit
      Wireless, aerospace and defense, instrumentation and medical imaging applications continue to drive demanding performance requirements for today's sophisticated electronic systems (+)

      Features:

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      • Due to their inherent hardware structure advantages, Xilinx FPGAs outstrip the high-end computing power of traditional digital signal processors
      • Based on the performance leading Virtex-6 FPGAs, this DSP Kit bundles pre-validated software tools, IP and hardware into a platform that addresses even the most challenging applications
      • With the addition of targeted reference designs, the Virtex-6 FPGA DSP kit enables users to focus on creating their own unique differentiation from the very beginning of the product development process, accelerating development for experienced users while also simplifying the adoption of FPGAs for new users
    • The XtremeDSP™ Starter Kit – Spartan®-3A DSP 1800A FPGA Edition
      Development board (+)

      Features:

      • Power supply 100-240 V, 50/60 Hz with universal plug adaptors
      • USB Platform download cable for configuration and debug
      • System Generator for DSP design software
    • Endpoint LogiCORE
      A solution consisting of Xilinx' Serial RapidIO Physical Layer core, Logical I/O and Transport Layer core, Register Manager Reference Design and Buffer Reference Design (+)

      Features:

      • Fully compliant with the RapidIO Serial Interconnect Specification v1.3 from the RapidIO Trade Association
      • Physical Layer supports one and four lanes operating with 64-bit internal data path
      • Supports 1.25, 2.5, and 3.125 Gbps line speeds
    • FPGAs for DSP
      Virtex-4 FPGAs for highest performance DSP (+)

      Features:

      • Up to 512, 500 MHz
      • XtremeDSP Slices (18 x 18 multiply, 48-bit add)\
      • Virtex-4 for lowest power per channel – each XtremeDSP Slice consumes only 2.3 mW per 100 MHz
    • Xilinx Spartan-6 FPGA Connectivity Development Kit
      RoHS-compliant SP605 board with Spartan-6 LX45T FPGA device, universal power supply, and accessory cables (+)

      Features:

      42978.jpg
      • ISE Design Suite Logic Edition tailored for logic and connectivity designers (device locked Spartan-6 LX45T FPGA)
      • PCIe-DMA-DDR3-Gigabit Ethernet targeted reference design
      • Example designs including hard memory controller and iBERT
    • Zynq-7000 EPP ZC702 Evaluation Kit
      Powerful Evaluation Kit for The Xilinx Zynq-7000 Extensible Processing Platform “All Programmable” SoC (+)

      Features:

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      • ROHS compliant ZC702 kit including the XC7Z020-CLG484-1 EPP Power 12V wall adapter or ATX voltage and current measurement capability of supplies
      • AMS Evaluation Board
      • Configurations: Onboard configuration circuitry, 16MB Quad SPI Flash, SDIO Card Interface (boot), PC4 and 20 pin JTAG ports
    • Xilinx Virtex-6 FPGA Embedded Kit
      RoHS-compliant ML605 board with Virtex-6 LX240T device, universal power supply, and accessory cables (+)

      Features:

      42979.jpg
      • ISE Design Suite Embedded Edition with Platform Studio tools, EDK, and SDK (device locked Virtex-6 LX240T FPGA)
      • Customizable base processor reference design with MicroBlaze processor and Linux support
      • Example designs including iBERT, system monitor, and DDR3
  • ProPlus Solutions  (1)
    • BSIMProPlus, NanoSpice, NanoYield
      BSIMProPlus is the industry’s leading SPICE modeling platform adopted by most semiconductor companies as the de facto golden SPICE solution for over 10 years; NanoSpice is a new generation full chip parallel SPICE simulator that can significantly improve circuit simulation performance at full SPICE accuracy; NanoYield is innovative design-for-yield software for yield analysis and design optimization. (+)

      Features:

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      • BSIMProPlus: Provides the most complete modeling flows for modeling engineers and supports all device types, all public-domain models and different model types, including DC, AC, RF, Noise, Reliability, Statistical, Stress, etc. It also provides complete device evaluation, model validation and customization functions for CAD and design engineers.
      • NanoSpice: With one single engine that can handle scalable circuit size up to over ten millions of elements for generic circuit types and over 100 million of elements for memory circuits, at SPICE accuracy, it supports industry standard inputs/outputs and provides an easy, fast and reliable way for circuit simulation and verification.
      • NanoYield: Is the industry’s only solution integrating device modeling, parallel SPICE simulation and statistical analysis, and provides fast and accurate 3-6 sigma statistical analysis, yield prediction and optimizations for memory, logic, analog and digital circuit designs. [...]
  • Aptix Corp.  (1)
    • Expedition
      An interactive environment enabling creation of prototypes for system-on-chip (SoC) devices directly from Register Transfer-Level (RTL) designs (+)

      Features:

      • Expedition emulation software, automates the RTL design mapping process allowing users to focus on verifying and debugging SoC designs
      • The package is a front-end tool for Aptix's System Explorer prototyping tools, shich map RTL design descriptions for FPGA logic netlists
      • Simple-to-use graphical user interface built on Java technology
11/5/17 08:39
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