Embedded Software
-
Verific Acquires INVIO Platform from Invionics Software
Rapid Application Development Platform will be added to Verific’s Parser Platform
-
Verific Signs Licensing Agreement with Functional Safety Solutions Provider Austemper Design Systems
Parser Platform Serves as Front End to Austemper’s Functional Safety Tool Suite
-
Verific Adds UPF Elaborator to Comprehensive Parser Platform Portfolio
New Functionality Broadens UPF Parser/Analyzer Capabilities
-
Verific Design Automation’s Parser Platform Integrated With Tortuga Logic’s Hardware Security Design and Analysis Toolkit
Thoroughly Tested Parsers Let Tortuga Logic Focus on Software to Identify Security Vulnerabilities in Hardware Designs
-
Vtool Relies on Verific Design Automation’s Parser Platform to Drive Disruptive, Functional Verification Platform
Verific’s Parser Platform Ensures Integration With SystemVerilog and UVM
-
Verific Invites DAC Attendees to Visit Booth for Giraffe Giveaway, Learn About SystemVerilog, VHDL, UPF Parser Platforms
Verific Invites DAC Attendees to Visit Booth for Giraffe Giveaway, Learn About SystemVerilog, VHDL, UPF Parser Platforms
Twenty-Four Partners Exhibiting at DAC
-
Verific’s SystemVerilog, VHDL Parsers Chosen by Flexras Technologies to Serve as Front End for FPGA-Based Prototyping Tool
High-Quality Technology, Superior Support, Service Cited in Flexras’ Decision
-
Menta Follows FPGA Leaders by Selecting Verific for its SystemVerilog, VHDL Front End
Menta Origami Designer Used to Create Embedded FPGAs in SoC Designs
-
Verific Design Automation’s Industry-Standard SystemVerilog, VHDL Parsers Linked With Aldec’s Hardware Emulation Solution
Companies Sign Licensing Agreement
-
Verific Exhibits at 49th Design Automation Conference and Hosts DAC Tuesday Night Reception
Promotes "Build Your Own RTL Tools" for SoC Designers
