Altera announces SoC FPGAs with dual-core ARM Cortex A9 and virtual prototyping support

October 11, 2011 — Mike Demler, Editorial Director

Altera has announced development of a family of ARM-based SoC FPGAs, which will provide users with single-chip solutions that integrate a dual-core ARM Cortex-A9 processor with Altera’s low power Cyclone V and Arria V FPGA fabrics. Todd Koelling, Sr. Product Marketing Manager for Embedded Processors at Altera, says that the SoC FPGA processor system will be based on a industrial grade dual-core 800MHz ARM Cortex-A9 MPCore processor, which the company will fabricate in a 28nm low-power process (28LP).

Each core in the Altera SoC FPGA processor system includes a ARM NEON media processing engine, and a single/double-precision floating point unit with 32KB/32KB  (instruction/data) of L1 cache per core.  The pair of processors share a error correcting code (ECC) protected 512-KB L2 cache. Additional hard IP in the SoC FPGAs will include up to three multi-port memory controllers with ECC for DDR2/3, Mobile DDR, and LPDDR2 memories. For Flash memories, the SoC FPGAs include a queued serial peripheral interface (QSPI) for NOR, and a NAND controller, both with ECC. Koelling says that the addition of ECC to the memory interfaces, which is usually omitted from PC applications, is critical to address signal integrity issues in high speed data transmission for industrial and military applications.

The SoC FPGAs also provide up to two PCIe Gen 2 x4 interfaces as hard IP, and soft IP is available for users who require x8 configurations of PCIe.

Altera's SoC FPGA integrates a dual-core ARM Cortex-A9 processor system with the low power Cyclone V and Arria V FPGA fabrics
Altera has designed the SoC FPGA so that the processor system and FPGA fabric are powered independently, so that users can configure and boot the device in any order. Once in operation, users can power down the FPGA as needed to conserve system power.  The ARM Cortex-A9 MPCore processor system and FPGA fabric connect through ARM’s AXI interface, which Altera has configured as 256b bi-directional data paths at 200MHz (Cyclone) and 250MHz (Arria), for a peak bandwidth capability of greater than 125-Gbps with integrated data coherency. According to Altera, the processor system can deliver 4,000 DMIPS peak performance with less than 1.8 watts power consumption.

Altera's SoC FPGA family will offer a range of four Cyclone V based products and two Arria V devices.
Altera has employed the ARM accelerator coherence port (ACP), so that users can implement accelerators in the SoC FPGA fabric that are cache coherent with the processor subsystem. Koelling says that use of the ACP increases system performance, which Altera has specified at up to 1,600 billion multiply-accumulate operations (GMACS) and 300 billion floating point operations (GFLOPS) from the variable precision block.  The product family will include four lower end Cyclone devices, and two higher end Arria devices, offering a choice of performance and total power consumption from 2W (single core at 300MHz, commercial temperature range) to 15W (dual core at 800MHz, industrial temperature range).

Altera is also announcing a new development system for the SoC FPGAs, which the company  has dubbed a Virtual Target, based on ' virtual prototyping solutions. Hardware designers will still be able to use Altera’s Quartus II design software, and the Qsys system integration tool. Software designers will be able to perform immediate device-specific for the SoC FPGA devices, prior to availability of silicon. According to Altera, the Virtual Target is a binary- and register-compatible, functional equivalent of an SoC FPGA board, which will enable users to transfer software developed on the Virtual Target to the actual board with minimal effort.

Altera is supporting and the Wind River   () in the Virtual Target, and software engineers can also continue to employ the ecosystem of ARM development tools. The Virtual Target includes the same processor and system peripherals that will be in the Cyclone V and Arria V SoC FPGAs, along with real board-level I/O connectivity to a host PC, including DDR SDRAM, Ethernet, USB and flash memory. Altera is also planning to offer an optional FPGA-in-the-loop extension to the Virtual Target, which will enable users to connect an Altera FPGA development board to the PC-based Virtual Target over a PCIe interface, for development of customer-designed FPGA-based IP.

Pricing and Availability

The SoC FPGA Virtual Target is available now for purchase from Altera.  Koelling says that Altera has worked with Synopsys to specifically adapt the Synopsys Innovator platform to the SoC FPGAs. The resulting solution will be sold by Altera as a complete turnkey solution, and it will include a seat of the Synopsys Innovator development environment. Altera is planning to have the FPGA-in-the-loop extension available early next year. Free downloads of a prebuilt GNU tool chain and Linux source also are available from Altera. A VxWorks board support package (BSP) will be available this quarter (Q4 2011) for the Virtual Target, and Altera plans to develop more BSPs for other embedded operating systems.

Altera is targeting  the second half of 2012 for availability of SoC FPGA silicon will be available, and reference designs and development boards will follow.  Pricing for Altera’s SoC FPGAs will start at less than $15 in high volumes.


Subscribe to FPGA updates