FPGA

Focus shifts to software for FPGA SoCs at DESIGN West

April 19, 2012 — Mike Demler, Editorial Director

Though the has now been renamed to , the 2012 event was once again a great venue for catching up on the latest technology for programmable embedded applications from leading vendors. Manufacturers are now shipping production silicon for some of the FPGA SoCs they announced over the last year, which embed various configurations of ARM Cortex processor cores with programmable logic and / blocks. While these new devices offer designers a great deal of flexibility for implementing an embedded system, they also present a new set of challenges, especially in how to optimize hardware-software partitioning. A number of the DESIGN West demonstrations, presentations, and announcements were targeted at solutions for these issues, with a focus on the software tools that will be required to successfully employ FPGA SoCs.

New solutions to ease programming of FPGAs

The Open Computing Language (OpenCL) is a C-based open standard for parallel programming of heterogeneous systems, which often include a mix of CPUs, GPUs, DSPs, and specialized hardware accelerators. Apple Inc., the original creator of OpenCL, worked with AMD, IBM, Intel, and NVIDIA to submit it as an open, royalty-free standard, to be maintained by the not-for-profit industry consortium Khronos Group in 2008. As Khronos describes it, “OpenCL consists of an API for coordinating parallel computation across heterogeneous processors, and a cross-platform programming language with a well-specified computation environment.”

This description of heterogeneous systems also applies to the new generation of SoC-like architectures that have been introduced by Altera, Xilinx, and Microsemi, with the CPU being one or more ARM cores, and the parallel computational capabilities provided by the programmable FPGA logic. OpenCL offers a possible solution to one of the major hurdles of adopting FPGA SoC devices: the incompatibility of HDL-based FPGA design methodologies used by hardware engineers with the C language programming model used by software engineers. To address this, Altera started a development program in November 2011 to extend the OpenCL standard to FPGA SoCs.

At DESIGN West, Altera demonstrated a methodology for using OpenCL to partition system designs between a host processor and FPGA. To increase system performance, software architects can profile their C/C++ code to identify the portions that would benefit from OpenCL’s ability to transfer execution of multiple parallel instances of "kernel" code to FPGA accelerators. To make the design flow easy to use, FPGA manufacturers must provide OpenCL compilers for their target devices. The OpenCL compiler generates the code needed to drive Electronic System Level (ESL) tools, such as Altera’s Quartus or Xilinx’s AutoESL tools. The ESL tools would, in turn, generate HDL code for gate-level synthesis of the FPGA hardware in the background.

While not yet offering an OpenCL product, Altera has described some successful applications. The company says that goHDR, a manufacturer of High Dynamic Range (HDR) video cameras, was able to port their proprietary video codec to OpenCL while continuing to work entirely in a C language environment. With Altera’s OpenCL-to-ESL flow, goHDR was able to implement an FPGA in less than a week. The companies estimate that design process using a traditional HDL flow would have taken several months.

Hardware-software partitioning enables low-power design

Microsemi’s SmartFusion cSoC integrates a flash-based FPGA fabric with a 100 MHz ARM Cortex-M3 Microcontroller Subsystem (MSS) and programmable analog function blocks. In a paper and presentation at DESIGN West (“Power Aware Hardware/Software Partitioning on a Customizable System-on-Chip (cSoC) Platform”), Mir Sayed Ali, Senior Staff Applications Engineer in Microsemi's SoC product group, described how hardware-software partitioning in an FPGA SoC can be used to optimize system power dissipation as well as performance.

As in Altera’s OpenCL flow, the Microsemi low-power design methodology requires system engineers to profile their software in order to identify which tasks consume the most energy. Microsemi recommends use of a tool like the IAR Embedded Workbench for ARM, which can estimate the percentage of energy consumed by individual functions in a system’s application code. Higher energy tasks then become candidates for implementation in the cSoC programmable logic cells. Microsemi also provides their SmartPower tool that enables designers to estimate power from simulations of the hardware implementation prior to testing on actual hardware.

This process of hardware-software partitioning is manual and iterative since there is no assurance that a significant power saving can be achieved, especially for tasks which require a high level of bus activity. To aid in the development of low-power designs, Microsemi offers a set of best-practice suggestions for software developers. As an example, Microsemi advises utilizing interrupt-driven functionality, rather than polling by software. They also suggest using on-chip Direct Memory Access (DMA) for bulk data transfer, and keeping the processor in sleep mode during such idle time operations.

Dual-core FPGA SoCs increase options for embedded operating systems

Xilinx’s version of an FPGA SoC, the Zynq-7000 Extensible Processing Platform (EPP), was featured at the company’s DESIGN West exhibit with a dozen different hardware-software demonstrations. A number of the demonstrations addressed another critical software component: the need to support the commercial embedded operating systems that developers use today, if ARM-powered are to compete with standalone Microcontrollers (MCUs) and Microprocessors (MPUs).

For many embedded applications, designers will need to employ a Real-Time Operating System (RTOS). At DESIGN West, Xilinx and Wind River announced that the VxWorks RTOS and Wind River would be added to the list of operating systems that are supported on Zynq. With dual ARM Cortex-A9 cores on the Zynq-7000, software architects can apply the VxWorks RTOS in either a Symmetrical Multi-Processing (SMP) or Asymmetrical Multi-Processing (AMP) mode, or as a guest operating system with the WindRiver .

Adeneo Embedded also announced RTOS support for Zynq at DESIGN West, with a Board Support Package (BSP) that enables users to develop applications with the Microsoft Windows Compact 7 operating system. The Adeneo BSP supports SMP mode and the Open Graphic Library (OpenGL) for Embedded Systems (ES1.1) standard. Xilinx also supports the FreeRTOS in AMP mode, with FreeRTOS running on both cores or with FreeRTOS on one core and Linux on the other. Xilinx also supports version 2.3 () on the Zynq platform, with downloadable source files that enable use of the display controller and OpenGL for Embedded Systems (ES 1.1)-based graphics accelerator that is integrated into these devices. The benefit of the FPGA SoC platforms for software developers is that their processor systems should be bootable without the need to configure the FPGA logic. With Linux, Windows, RTOS, and Android available, engineers will have the flexibility to develop a wide variety of embedded applications using the software tools they are already accustomed to.

More embedded cores in FPGA’s future?

With the new generation of embedded ARM-based architectures, FPGAs are following the same path as ASIC SoCs – from single-core to dual-core devices. Will quad cores be next? Or will we see an FPGA version of ARM’s “big.LITTLE” architecture, which combines one core for performance with another, smaller core for power efficiency? If the FPGA vendors succeed in creating efficient hardware-software design methodologies, this could be just the beginning for the evolution of FPGAs into heterogeneous parallel programmable devices.

Close

Subscribe to FPGA updates