Xilinx CTO makes case for the value of programmability in SEMICON West keynote

July 13, 2012 — Mike Demler, Editorial Director

At the SEMICON West tradeshow in San Francisco this week, Ivo Bolsens, Senior Vice President & Chief Technology Officer at Xilinx, delivered a keynote address titled "All Programmable – from Silicon to System".  In his presentation to this semiconductor manufacturing industry audience, Dr. Bolsens made his case for how a fabless company such as Xilinx can work with the ecosystem to leverage Moore's Law and deliver greater value to system design customers.

Bolsens offered his opinion that the fabless companies which survive will be those that are more collaborative throughout the semiconductor design chain.  He said that Xilinx has been engaging earlier and and more deeply with both partners and customers. As an example, Bolsens said that his company's efforts in 3D/2.5D packaging began more than five years ago, with what were then essentially "science experiments" in which Xilinx engaged not with foundries, but with semiconductor equipment manufacturers.

According to Bolsens, success is now measured by adding value to systems for companies like Ericsson and Cisco, rather than by cost reduction.  For Xilinx, two keys to delivering such value are through greater programmability and 3D integration. Bolsens began his presentation by describing several different dimensions of the value of programmability.

Programmability of memory

The first measure was based on the system value of programmable memory. On one extreme, Bolsens pointed to the example of Google's storage, which is offered to most users essentially free of charge. In comparing memory in to standalone SRAMs, he admitted that by a conventional measure such as $/GB, FPGAs are orders of magnitude more expensive.  Why then, would customers be willing to pay more, he asked rhetorically? For Xilinx, the answer comes down flexibility.

Bolsens' argument is that FPGA users benefit in the use of FPGA memory because they can choose their memory depth, word length, and even latency.  That flexibility is of value, he said, along with the opportunity for greater bandwidth.  By converting the measure of value to total Gb/sec, the parallelism and I/O configurability of FPGAs can be shown to provide an advantage over standalone memory.

The value of configurability

The second dimension of of the Xilinx value proposition at SEMICON was the inherent configurability of FPGAs. There is nothing new in this statement, but Bolsens added the argument that this configurability can lead to lower system power. He cited the example of a Xilinx customer who was building a platform, which required support for 29 different configurations.  Compared to building each of those configurations into custom hardware, and assuming that most of those configurations would not be needed simultaneously, the configurability of an FPGA would be more silicon-efficient, and hence lower in power and cost.

FPGAs, hardware acceleration and a call to the industry

There is also nothing new in the use of FPGAs for hardware acceleration of general-purpose CPUs. However, the new FPGA SoCs such as Xilinx Zynq,  provide additional flexibility in their hybrid single-chip implementation of  a ARM Cortex A9 processing system alongside a programmable FPGA fabric.  By moving functions from software to FPGA hardware, Bolsens claimed as much as 50X lower power can be achieved through more fine-grained programmability than in general purpose CPUs.

The challenge though, said Bolsens, is that the EDA industry must come to the rescue for users to be able to exploit that programmability.  FPGA SoCs offer so many different forms of programmability, in programmable logic, processors, I/O, etc., that new design methods must be developed that can exploit the available parallelism and heterogeneity.  Bolsens showed an example flow based on OpenCL, which Altera is also exploring, as one possible answer. With OpenCL, software developers could employ C-programming  for the ARM core processing subsystem, while (HLS) could convert C-language to HDL for configuring the FPGA.

Adding value through 3D integration

It was evident at SEMICON that the semiconductor manufacturing industry is continuing to struggle with a number of issues regarding the future for 3D IC integration. While some see 3D ICs as an inevitable alternative for extending Moore's Law, high cost, supply chain issues, a lack of standards, and the need for new design and test methods persist as major obstacles to mainstream adoption.

Xilinx has been at the forefront of 3D IC development, with their use of stacked-silicon interconnect (SSI) in their 2000T FPGA.  In May, Xilinx announced the H580T, combining FPGA die with separate die for 28 Gbps transceivers, in the same package.

In Bolsens' keynote, he pointed to 3D integration (or more accurately 2.5D), as a means of delivering value through higher functionality.  He made the point that the multi-die approach in the 2000T can overcome  the exponentially increasing yield loss as a result of silicon defect density, compared to an equivalent gate count monolithic implementation. It is not immediately obvious, though, that this yield loss would result in a higher cost than the additional manufacturing expense involved in the 2000T's multi-die silicon interposer process.

However, Bolsens also made the case for higher I/O bandwidth per watt in 2.5D/3D ICs.  By using a 65nm silicon interposer to connect the I/O, Xilinx can achieve more than 50K interconnects between die, resulting in 2.78Tb/s of connectivity. By pre-selecting known good die (KGD), the multi-chip approach can also overcome the problem of variability, which is especially problematic in more advanced process nodes, such as 28nm CMOS.

Bolsens ended with a call for the semiconductor industry to come together in order to further develop 3D IC technology. He called for more work in design enablement, development of manufacturing standards, and the need for multi-vendor silicon interoperability.


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