Xilinx has launched a new set of Targeted Design Platforms (TDP), at the 2102 National Association of Broadcasters (NAB) show in Las Vegas this week. The Display TDP supports development of content for emerging quad High Definition 4K2K (Quad HD) displays. Aaron Behman, Senior Manager for Broadcast & Consumer Market Segments, says that Xilinx worked with alliance partner Tokyo Electron Device Ltd. on the Display TDP, which will be sold under the inrevium brand for $2,995. The Display TDP uses the 28nm Kintex-7 FPGA. Xilinx and TED include three reference designs with the Display TDP, including a mosaic design function which enables users to stitch together four individual 1920×1080 video streams into a single 4K2K display. Other reference designs are provided for performing standard HD to 4K2K up-conversion, and a 4K2K frame rate converter from 60Hz to 120Hz

Xilinx has also updated their Real-Time Video Engine (RTVE) TDP to the Kintex-7 FPGA. The new version adds the capability for dual processing video pipelines, for applications such as picture-in-picture. A new web GUI allows connecting to a LAN router for remote control of the TDP from a tablet, PC or smartphone. Xilinx targets the RTVE at applications in broadcast switchers and routers, multiviewers and display systems.

Xilinx designed a third set of TDPs for Edge Quadrature Amplitude Modulation (QAM) applications, in Hospitality QAM for hotel room Video-on-Demand (VoD), and Converged Cable Access Platforms (CCAP). Designers can add an FPGA Mezzanine Card (FMC) to the TDP, with Digital-Analog Converters (DACs) from Analog Devices (AD9739A) or Maxim Integrated Products (MAX5882). The Edge QAM TDP will be available with the Kintex-7 KC705 Base Board and Kintex-7 K325T FPGA, or the Virtex-7 VC707 Evaluation Board and Virtex-7 485T FPGA. Xilinx is also developing a Quad port version, which will employ dual Virtex-7 X485T/X690T FPGAs.

New solutions to ease programming of FPGAs

The Open Computing Language (OpenCL) is a C-based open standard for parallel programming of heterogeneous multicore systems, which often include a mix of CPUs, GPUs, DSPs, and specialized hardware accelerators. Apple Inc., the original creator of OpenCL, worked with AMD, IBM, Intel, and NVIDIA to submit it as an open, royalty-free standard, to be maintained by the not-for-profit industry consortium Khronos Group in 2008. As Khronos describes it, “OpenCL consists of an API for coordinating parallel computation across heterogeneous processors, and a cross-platform programming language with a well-specified computation environment.”

This description of heterogeneous systems also applies to the new generation of SoC-like architectures that have been introduced by Altera, Xilinx, and Microsemi, with the CPU being one or more ARM cores, and the parallel computational capabilities provided by the programmable FPGA logic. OpenCL offers a possible solution to one of the major hurdles of adopting FPGA SoC devices: the incompatibility of HDL-based FPGA design methodologies used by hardware engineers with the C language programming model used by software engineers. To address this, Altera started a development program in November 2011 to extend the OpenCL standard to FPGA SoCs.

At DESIGN West, Altera demonstrated a methodology for using OpenCL to partition system designs between a host processor and FPGA. To increase system performance, software architects can profile their C/C++ code to identify the portions that would benefit from OpenCL’s ability to transfer execution of multiple parallel instances of “kernel” code to FPGA accelerators. To make the design flow easy to use, FPGA manufacturers must provide OpenCL compilers for their target devices. The OpenCL compiler generates the code needed to drive Electronic System Level (ESL) tools, such as Altera’s Quartus or Xilinx’s AutoESL tools. The ESL tools would, in turn, generate HDL code for gate-level synthesis of the FPGA hardware in the background.

While not yet offering an OpenCL product, Altera has described some successful applications. The company says that goHDR, a manufacturer of High Dynamic Range (HDR) video cameras, was able to port their proprietary video codec to OpenCL while continuing to work entirely in a C language environment. With Altera’s OpenCL-to-ESL flow, goHDR was able to implement an FPGA in less than a week. The companies estimate that design process using a traditional HDL flow would have taken several months.

Hardware-software partitioning enables low-power design

Microsemi’s SmartFusion cSoC integrates a flash-based FPGA fabric with a 100 MHz ARM Cortex-M3 Microcontroller Subsystem (MSS) and programmable analog function blocks. In a paper and presentation at DESIGN West (“Power Aware Hardware/Software Partitioning on a Customizable System-on-Chip (cSoC) Platform”), Mir Sayed Ali, Senior Staff Applications Engineer in Microsemi’s SoC product group, described how hardware-software partitioning in an FPGA SoC can be used to optimize system power dissipation as well as performance.

As in Altera’s OpenCL flow, the Microsemi low-power design methodology requires system engineers to profile their software in order to identify which tasks consume the most energy. Microsemi recommends use of a tool like the IAR Embedded Workbench for ARM, which can estimate the percentage of energy consumed by individual functions in a system’s application code. Higher energy tasks then become candidates for implementation in the cSoC programmable logic cells. Microsemi also provides their SmartPower tool that enables designers to estimate power from simulations of the hardware implementation prior to testing on actual hardware.

This process of hardware-software partitioning is manual and iterative since there is no assurance that a significant power saving can be achieved, especially for tasks which require a high level of bus activity. To aid in the development of low-power designs, Microsemi offers a set of best-practice suggestions for software developers. As an example, Microsemi advises utilizing interrupt-driven functionality, rather than polling by software. They also suggest using on-chip Direct Memory Access (DMA) for bulk data transfer, and keeping the processor in sleep mode during such idle time operations.

Dual-core FPGA SoCs increase options for embedded operating systems

Xilinx’s version of an FPGA SoC, the Zynq-7000 Extensible Processing Platform (EPP), was featured at the company’s DESIGN West exhibit with a dozen different hardware-software demonstrations. A number of the demonstrations addressed another critical software component: the need to support the commercial embedded operating systems that developers use today, if ARM-powered FPGAs are to compete with standalone Microcontrollers (MCUs) and Microprocessors (MPUs).

For many embedded applications, designers will need to employ a Real-Time Operating System (RTOS). At DESIGN West, Xilinx and Wind River announced that the VxWorks RTOS and Wind River Linux would be added to the list of operating systems that are supported on Zynq. With dual ARM Cortex-A9 cores on the Zynq-7000, software architects can apply the VxWorks RTOS in either a Symmetrical Multi-Processing (SMP) or Asymmetrical Multi-Processing (AMP) mode, or as a guest operating system with the WindRiver Hypervisor.

Adeneo Embedded also announced RTOS support for Zynq at DESIGN West, with a Board Support Package (BSP) that enables users to develop applications with the Microsoft Windows Compact 7 operating system. The Adeneo BSP supports SMP mode and the Open Graphic Library (OpenGL) for Embedded Systems (ES1.1) standard. Xilinx also supports the FreeRTOS in AMP mode, with FreeRTOS running on both cores or with FreeRTOS on one core and Linux on the other. Xilinx also supports Android version 2.3 (Gingerbread) on the Zynq platform, with downloadable source files that enable use of the display controller and OpenGL for Embedded Systems (ES 1.1)-based graphics accelerator that is integrated into these devices. The benefit of the FPGA SoC platforms for software developers is that their processor systems should be bootable without the need to configure the FPGA logic. With Linux, Windows, RTOS, and Android available, engineers will have the flexibility to develop a wide variety of embedded applications using the software tools they are already accustomed to.

More embedded cores in FPGA’s future?

With the new generation of embedded ARM-based architectures, FPGAs are following the same path as ASIC SoCs – from single-core to dual-core devices. Will quad cores be next? Or will we see an FPGA version of ARM’s “big.LITTLE” architecture, which combines one core for performance with another, smaller core for power efficiency? If the FPGA vendors succeed in creating efficient hardware-software design methodologies, this could be just the beginning for the evolution of FPGAs into heterogeneous parallel programmable devices.

The Xilinx Virtex-7 VC707 Evaluation Kit

Xilinx has announced availability of the first design kits and Targeted Design Platform (TDP) for the company’s latest 28nm Kintex-7 and Virtex-7 FPGAs.  The kits were developed through a close partnership between Xilinx and their Alliance Members – 4DSP Inc., Analog Devices Inc., Avnet Electronics Marketing, Northwest Logic, MathWorks, Texas Instruments, and Xylon.

According to Mark Moran, Senior Marketing Manager at Xilinx, the kits that the company is announcing at the 2012 DesignCon  are just the first of 40 that will be developed by the company and its partners.

The first three Xilinx Series 7 kits are:

• The Kintex-7 FPGA KC705 Evaluation Kit for designing higher-level systems that employ DDR3, Gigabit Ethernet, PCI Express, and other serial connectivity standards. Communications features include high-speed GTX transceivers, with enhanced small form-factor pluggable (SFP+) and SubMiniature version A (SMA) connectors.
  • Price and availability: $1,695 order entry open now.

• The Kintex-7 FPGA DSP Kit co-developed with Avnet Electronics Marketing features the Kintex-7 FPGA KC705 board and includes an integrated high-speed analog FPGA Mezzanine Card (FMC) to interface to real-world signals. The DSP Kit includes dual-channel 800 MSPS 16-bit digital-to-analog converters (DACs) and dual-channel 250 MSPS 14-bit analog-to-digital converters (ADCs), which designers can combine with the DSP48E1 arithmetic processing engines in the Kintex-7 FPGA. Data paths to and from the DSP slices can be created and integrated into systems using industry-standard AXI4 interface conventions.
  • Price and availability: $3,995 order entry now from Avnet.

• The Virtex-7 FPGA VC707 Evaluation Kit gives designers of advanced systems with high performance and high bandwidth connectivity requirements a starting point for evaluating Virtex-7 FPGAs, which require 50 percent less power than previous generation devices.
  • Price and availability: $3,495 with order entry open late-February 2012.

To enable the addition of peripherals to the base Xilinx development boards, each kit supports the VITA 57 FMC specification for the industry standard daughter card form factor, connector and modular interface to the FPGA.  The Xilinx Agile Mixed Signal (AMS) header is provided with all 7-Series kits, along with board design files, and a full seat of the Xilinx ISE Design Suite Logic Edition, locked to the on-board FPGA.

The Kintex-7 KC705 kit comes with a set of reference designs on a USB Flash Drive; a built-in self test (BIST) board diagnostic test design, Integrated Bit Error Ratio Tester (IBERT) transceiver (XCVR), Multi-Boot reference design, DDR3 memory interface, PCIe x4 Gen2 PIO, AMS reference design, and a PCIe/DDR3 targeted reference design supporting x4 Gen 2 and DDR3 at 1600Mbps.

To assist in developing applications with the Kintex-7 DSP Kit, Xilinx includes a copy of MathWorks evaluation software for MATLAB and Simulink. A reference DSP design is downloadable from Avnet.

With the Virtex-7 Evaluaiton Kit, Xilinx is also providing a set of reference designs for PCI Express x8 Gen2 design, DDR3 Memory Interface, Gigabit and 10Gigabit Ethernet, BIST board diagnostics, and the IBERT XCVR test design.

Xilinx has updated their Virtex-6 Broadcasting Connectivity kit for SMPTE 2022-5/-6

At the opening of the broadcast industry’s IBC conference in Amsterdam today, Xilinx announced availability of enhancements to their real-time video engine intellectual property cores,  with the addition of support for the -5 and -6 revisions of the Society of Motion Picture & Television Engineers (SMPTE) 2022 standard for transporting uncompressed High-Definition (HD) and 3D high-resolution video packets over internet protocol (IP) networks. SMPTE 2022-5 defines specifications for “Forward Error Correction for High Bit Rate Media Transport over IP Networks”, and SMPTE 2022-6 addresses “High Bit Rate Media Transport over IP Networks”.

Robert Green, Broadcast Marketing Manager at Xilinx, says that the company has enhanced their SMPTE core with features for Forward Error Correction (FEC) which enable recovery of packets that may get lost during transmission, delivering better quality of service (QoS).

In a typical live TV production scenario today, digital video cameras are used to stream data to a broadcast truck over the SMPTE Serial Digital Interface (SDI), for transmission over satellite links back to studio engineers. By using a bridge that incorporates Xilinx FPGAs, and combining the 2022-5/-6 cores with 10Gb ethernet (10GbE) I/Os, engineers can transmit video over IP directly to the studio. Video over IP eliminates the cost of rolling trucks and heavy cables at an event, offering a more “green” solution for lower environmental impact.

The hardware acceleration provided by the Xilinx SMPTE cores also enables real-time high-definition (HD) video editing, increasing productivity for in-studio or remote use. Xilinx has incorporated the 2022 cores into their Virtex-6 FPGA Broadcast Connectivity Kit (V6BCK), with a system-level reference design that allows user customization on top of the pre-designed components.

The Xilinx SMPTE 2022 cores are scalable to the company’s 40nm Virtex-6 and 28nm Kintex-7 families of FPGAs. The Virtex-6 implementation, which is available now for early access, can support nine 3Gbps SDI inputs, streaming out through three sets of 4X XAUI interfaces at 2.56Gbps per I/O to a total of three off-chip 10GbE PHYs. The Kintex-7 implementation of SMPTE 2022, which Xilinx is planning for availability next year, will expand on that capability by enabling the use of twelve 3Gbps SDI inputs, and replacing the the 4x XAUI I/O with a single serializer-deserializer (SERDES) for Xilinx’s 10GbE GTX transceivers. The Kintex-7 will be capable of supporting 12.5 Gbps line rates for an increase of 2x in system bandwidth.