It is important to remember that all codecs have their upsides and downsides. In considering any single algorithm for use the system architect must be aware of all factors and also that it is unlikely that any one codec will be completely ideal for its intended application. Limitations on the bandwidth of any network being used are a very important consideration.

In order to get some real world metrics for compression quality versus file size for each of the codecs, a test setup was created to encode various types of material at different compression rates, such that the resultant files could be examined for both size and video quality after being decompressed.

This white paper has been written to examine two of the more popular video codec technologies, MPEG-4 Part 10 (also known as Advanced Video Coding (AVC) and ITU-T H.264) and JPEG2000.

Annapolis Micro Systems product demonstration by Vice President of Sales Patrick Stover. Annapolis Micro Systems is the leader in COTS FPGA-based high performance computing board level products. Among Annapolis’ leading computing products are the CoreFire and Wildstar family of products.

Reconfigurable Computing uses Field Programmable Gate Arrays (FPGAs) as attached processing elements in a computing system, in order to dramatically increase the processing speed. Annapolis Micro Systems’ products include support for:
–Bus Options: VME, PCI, CompactPCI, PMC and PCMCIA;
–I/O options: Dual 1.5 / 2.3 GSps DAC, Dual 1.5 GHz A/D, 1/5 GHz A/D Pro, 1.5 GHz A/D, Quad 105 MHz A/D, 10 Gigabit Ethernet, Infiniband, Quad Fibre Channel 2, WILDSTAR Data Port (WSDP), FPDP, Fiber Optic GLINK, 80 MH A/D, Race and Race++ and others.

Annapolis Micro Systems is committed to helping its customers achieve their goals, with new CoreFire Design Suite, API and drivers, libraries, training classes, custom application development, and hourly support.

The company’s international customer base includes government labs, prime contractors, small companies, and universities.

Annapolis Micro Systems, Inc. was founded in May 1982 to provide electronic R&D and product design, custom hardware, software and systems design and manufacturing.

As an electronic design company, Annapolis Micro Systems, Inc. invented and developed a variety of electronic products for customers, such as IBM, Schlumberger, Alcatel Data Networks, Ericsson-GE, Computer Sciences Corporation, and the US. Government.

Annapolis Micro Systems, Inc. has earned a reputation for excellence in the areas of custom XILINX FPGA Design, system design, application development, ASIC design, complex printed circuit board design, surface mount assembly, and customer support.

Visit Annapolis at www.annapmicro.com

Video demonstration created by OpenSystems Media, www.opensystemsmedia.com and Vance Studios Productions.

When working on projects with large codebases that re-use components, it can be hard to identify which projects and products are affected by defects in shared code. How do you understand the impact of defects in your shared components? How do you analyze and prioritize the defects in your shared components so you know what to fix first, or not at all? How do you effectively track defect status and history across shared code?

Attend this webcast and you will learn five steps you can take to make the process of finding and fixing defects across shared code more efficient to increase developer productivity and reduce the risk of a schedule slip.

In this 30 minutes session you will learn:
• How to effectively scan your software to identify hard to spot defects in shared code
• How to identify which projects and products are impacted by defects to prioritize which defects should be fixed first
• What actions and best practices are needed to ensure the necessary fixes are implemented to prevent defects from entering the field

Designers can use Cypress’s new CY8CKIT-023 PSoC Expansion Board Kit For iPhone & iPod Accessories – a plug-in board to Cypress’s CY8CKIT-001 PSoC Platform Development Kit – to streamline design of innovative mobile accessories using the flexible PSoC programmable system-on-chip architecture. The new kit leverages the iPhone OS operating system of Apple’s iPhone and iPod products and the corresponding iPhone SDK (Software Development Kit) to provide a two-way communication interface between apps from Apple’s App Store and corresponding accessories.

Chances are protecting legacy investments is in your field of vision, even as new challenges arise. RadiSys product line manager John Long gives us an overview of how the ATCA-4850, ATCA-4550, and ATCA-4555 single board computers fit into the picture.

A video comprising footage from a drone UAV with Z Microsystems’ applied image enhancement algorithms performed on incoming SD or HD video streams using FPGAs. The coprocessing logic adds no additional latency but dramatically enhances the operator’s ability to extract information from the image. Since ISR platforms are designed to turn information into action, the image enhancement is practically a no-brainer “gotta have.” For comparison purposes, operators can turn image functions on or off with the click of a button. More videos and info are available from Z Microsystems at www.zmicro.com.

It appears that Curtiss-Wright Controls Embedded Computing (CWCEC) and Hybricon beat others to the punch with the first public demo of a working OpenVPX system. Demoed at the 2009 MILCOM military show in Boston, MA in October 2009.

SoftScan brings GPU acceleration to radar scan conversion applications. SoftScan uses a unique GPU-based algorithm that performs high-resolution scan conversion on large polar stores with minimal CPU overhead and requires no specialized hardware. Even when rendering multiple channels of radar video (from radars, network or synthetic sources) CPU load is kept to a minimum.

Supporting polar format radar video input either directly from radar acquisition hardware or distributed via network, SoftScan outputs radar display data in a number of formats including Plan Position Indicator (PPI), A-Scan and B-Scan. SoftScan utilizes the signal processing power available in modern GPUs to provide powerful algorithms that ensure there are no holes or spokes in the displayed image, even when zooming-in at long range, and that all single point targets are displayed. As well as displaying traditional plan views of radar, SoftScan allows radar images to be shown in real-time as projections from different origins and angles.

The USB-powered Beagle Board is a low-cost, fan-less single board computer utilizing Texas Instruments’ OMAP3530 application processor that unleashes laptop-like performance and expansion without the bulk, expense, or noise of typical desktop machines.

The Audience Voice Processor is the first integrated circuit that is modeled after the most efficient and accurate auditory system, the human hearing system. By understanding the auditory pathway – from the cochlea to the brainstem to the thalamus and cortex – Audience is the first company to deliver a commercial product based on the science of Auditory Scene Analysis (ASA), or the grouping and processing of complex mixtures of sound. Because the Audience Voice Processor handles signals the way people actually perceive specific sounds, Audience is able to identify and suppress noise sources in an extremely efficient and accurate manner.

Fast Cochlea Transform™
Just as the cochlea is central to the human auditory system, the Fast Cochlea Transform (FCT) is the heart of the Audience Voice Processor. The transformation provides optimum time-frequency resolution on a logarithmic frequency axis, without introducing frame artifacts, to allow the various components of the multiple sound sources to be characterized and separated from each other. The FCT’s transformation into the spectral domain is essential for Audience’s high-performance noise suppression because it permits regions of the frequency spectrum to be separately identified with different sound sources, even when they are present simultaneously.

SystemVue provides an instrument-grade algorithmic reference for FDD LTE, TD-LTE, and MIMO Physical Layer designs that follows you as you move from .m-file and C++ to VHDL/Verilog to finished hardware. By continuously-verifying your baseband PHY throughout the design process, you can meet aggressive time-to-market requirements, spend less on NRE, and improve your coverage and interoperability with an independent alogrithm/test-vector reference. Why wait until hardware to test your LTE algorithms? Achieve earlier design maturity & algorithmic pre-compliance using the LTE Baseband Libraries for Agilent SystemVue.

Design flow demonstration shows an LTE “scrambler” block moving from “.m-file” algorithm to VHDL verification.

In this 4-minute video, check out Altera’s new 40-nm FPGA demos showcasing 1.5-Gbps LVDS performance and an 8.5-Gbps transceiver operating with excellent signal integrity. You’ll watch eye diagrams demonstrating very low jitter, and how pre-emphasis and equalization improve signal integrity and allow for very long traces.

This device is ideal for products that need low power consumption whether portable or plugged. At a price of less than $10, it provides HD video performance and double the battery life of today’s HD products. In addition to providing a high level overview of the integral software components, he also highlights the corresponding development tools available to start designing today.

High Speed Digital Design expert Dr. Howard Johnson demonstrates how X2Y capacitors can be used to replace conventional bypass capacitors in FPGA designs. The result is dramatic cost savings through passive component reduction, fewer vias, and reduced board area.