FPGA

There are existing wideband communications systems that were built using field programmable gate array (FPGA)- based software defined radio (SDR) designs. Despite the inherent advantages of these systems, some are functionally restricted by limited output bandwidth. This thesis was conceived in order to mitigate the restrictions imposed on such designs. This was accomplished by designing an FPGA-based SDR that can compress sampled intermediate frequency (IF) signals. The compression scheme used in the final design is based on flexible operator-defined timefrequency bins and independent energy thresholds for each bin. The thesis presents basic design concepts that influenced the development process, the final design implementation created using Xilinx’s System Generator software, and the tests used to verify the final design’s functional capabilities.

In Software Defined Radios a good portion (or even the entirety) of the modulation and demodulation processes is performed in the digital domain. The data rate of the transmitted information is very important, since efficiency is a key requirement in real time implementations and cost increases considerably with the number of samples per second to be processed. In this thesis, we address the problem of efficient design of the resampling operations, so that they can be implemented on Field Programmable Gate Arrays (FPGAs). A set of filtering and resampling operations is developed in the Simulink environment through Xilinx/Simulink blocksets, where all the included subsystems of the design are fully accessible by the designer in any stage of operation. The key ingredient is the use of a Multiplier and Accumulator (MAC) architecture, which can be either time multiplexed for maximum hardware efficiency, or run on a parallel structure for maximum time efficiency.

This thesis presents an overarching plan to migrate a time-optimal spacecraft control algorithm from the MATLABTM development environment into an FPGA-based embedded-platform development board. Research at the Naval Postgraduate School has produced a revolutionary time-optimal spacecraft control algorithm based upon the Legendre Pseudospectral method. Currently, the control algorithm is dependent on the MATLABTM environment, a fourth generation language (4GL). 4GLs are powerful high-level abstraction and development tools, but are not efficiently instantiated into an embedded system. This study establishes three distinct development phases to migrate the algorithm from 4GL dependency to embedded operation. The first phase removes the algorithm’s dependency on the 4GL environment by translating the algorithm into the C programming language. The second development phase compiles and embeds the algorithm into an FPGA-based development board. The final development phase introduces a custom computing machine (CCM) instantiated in an FPGA to reduce the control calculation time, thereby broadening the algorithm’s potential application.

VHDL 101 is written for Electrical Engineers and others wishing to break into FPGA design and assumes a basic knowledge of digital design and some experience with engineering 'process'.

Bill Kafig, industry expert, swiftly brings the reader up to speed on techniques and functions commonly used in VHDL (VHSIC Hardware Description Language) as well as commands and data types. Extensive simple, complete designs accompany the content for maximum comprehension. The book concludes with a section on design re-use, which is of utmost importance to today's engineer who needs to meet a deadline and lower costs per unit.

*Gets you up to speed with VHDL fast, reducing time to market and driving down costs

* Companion website with source code and other documents to assist the student in building the reference design used throughout the book (http://www.elsevierdirect.com/companion.jsp?ISBN=9781856177047)

*Covers the basics including language concepts and includes complete design examples for ease of learning

* Covers widely accepted industry nomenclature

* Learn from "best design practices"

*Gets you up to speed with VHDL fast, reducing time to market and driving down costs

* Companion website with source code and other documents to assist the student in building the reference design used throughout the book

*Covers the basics including language concepts and includes complete design examples for ease of learning

* Covers widely accepted industry nomenclature

* Learn from "best design practices"

This book contains papers first presented at the Second International Workshop on Field-Programmable Logic and Applications (FPL '92), held in Vienna, Austria, in August-September 1992. The growing importance of field-programmable devices, especially of field-programmable gate arrays, is demonstrated by the increased number of papers submitted in 1992. Of the 70 papers submitted, 23 were selected for this book. The first three papers were invited and discuss strategic issues and give surveys. Three papers deal with new FPGA architectures and five papers introduce methods and tools. The last twelve papers report applications focusing on rapid prototyping or new FPGA-based computer architectures. The invited papers are: "Overview of complex array-based PLDs" by G. Biehl; "Technologies and utilization of field programmable gate arrays" by J. Isoaho, A. Nummela, and H. Tenhunen; and "Some considerations on field-programmable gate arrays and their impact on system design" by A. Sangiovanni-Vincentelli.

System-on-a-chip (SoC) has become an essential technique to lower product costs and maximize power efficiency, particularly as the mobility and size requirements of electronics continues to grow. It has therefore become increasingly important for electrical engineers to develop a strong understanding of the key stages of hardware description language (HDL) design flow based on cell-based libraries or field-programmable gate array (FPGA) devices. Honed and revised through years of classroom use, Lin focuses on developing, verifying, and synthesizing designs of practical digital systems using the most widely used hardware description Language: Verilog HDL. Explains how to perform synthesis and verification to achieve optimized synthesis results and compiler timesOffers complete coverage of Verilog syntaxIllustrates the entire design and verification flow using an FPGA case studyPresents real-world design examples such as LED and LCD displays, GPIO, UART, timers, and CPUsEmphasizes design/implementation tradeoff options, with coverage of ASICs and FPGAsProvides an introduction to design for testabilityGives readers deeper understanding by using problems and review questions in each chapterComes with downloadable Verilog HDL source code for most examples in the textIncludes presentation slides of all book figures for student reference 

Digital System Designs and Practices Using Verilog HDL and FPGAs is an ideal textbook for either fundamental or advanced digital design courses beyond the digital logic design level. Design engineers who want to become more proficient users of Verilog HDL as well as design FPGAs with greater speed and accuracy will find this book indispensable.

This book provides the advanced issues of FPGA design as the underlying theme of the work. In practice, an engineer typically needs to be mentored for several years before these principles are appropriately utilized. The topics that will be discussed in this book are essential to designing FPGA's beyond moderate complexity. The goal of the book is to present practical design techniques that are otherwise only available through mentorship and real-world experience.

This book describes the most important high-resolution NMR techniques that find use in the structure elucidation of organic molecules and the investigation of their behavior in solution.

The techniques are presented and explained using pictorial formats wherever possible, limiting the number of mathematical descriptions. The emphasis is on the more recently developed methods of solution-state NMR spectroscopy with a considerable amount of information on implementation and on the setting of critical parameters for anyone wishing to exploit these methods.

* presents a large number of examples to demonstrate the utility of the methods covered

* serves the needs of students and professionals in every chemistry laboratory

* describes the most important methods available, with guidance on execution of experiments

This thesis focuses on a software defined radio (SDR) designed to compress a wideband radio signal input for a narrowband signal output. The design is based on a Field Programmable Gate Array (FPGA), which is chosen for its
reprogrammability, flexibility, and our ability to introduce fault tolerance into the design. Software design tools allowed programming to be done at a high level, thereby allowing more progress on the design. This thesis focuses
on one such SDR that was designed at a high level of abstraction. This thesis documents an analysis of the memory and timing requirements of the circuit so that it may be used on resource-constrained FPGA devices. It also explores
the operating capabilities and limitations for this circuit under various resource-constrained conditions and introduces algorithms for fault detection to make the circuit more compatible with the space environment.