Osaka, Apr 23, 2012 – HuMANDATA LTD., a manufacturer of various FPGA/CPLD boards in Japan, today released EDX-301 of USB-FPGA board powered by Xilinx, Inc.’s Spartan-6LX FPGA (XC6SLX16-2CSG225C).

HuMANDATA’s EDX-301 is equipped with Xilinx high-spec Spartan-6LX FPGA on a compact, 53 x 54mm PCB. A configuration device, on-board oscillators, user switches and LEDs are mounted as minimum components of FPGA design and development. EDX-301 operates with 5.0 V external input or USB bus power. The EDX-301 provides 56 user I/Os, which are divided into two I/O banks. FTDI’s FT2232H (Dual channel USB controller IC) is equipped. One channel is available for a user communication interface. The other channel is configured as an I/F for FPGA configuration and configuration device access.

No download cable is needed with original configuration tool ” BBC [EDX-301]“.

HuMANDATA’s ACM/XCM series boards are designed on same PCB size and connector layout. So it is easy to swap the board to another one, and you can quickly try a new FPGA/CPLD.

HuMANDATA’s EDX-301 is compliant with the RoHS Directive, and is designed for lead-free soldering.

For more information, please visit: www.hdl.co.jp/en/index.php?id=215

Specifications:

- XILINX Spartan-6 (XC6SLX16-2CSG225C) 

- Configuration Device(Micron, M25P16-VMN) 

- USB control IC (FTDI, FT2232H) 

– FPGA Configuration 

– Configuration device access (Write/Reset/Erase) 

– User communication I/F 

– Free original configuration Tool ” BBC [EDX-301]“ 

- 50MHz Oscillator (50 ppm) or External inputs 

- User Switch (Push x1, DIP x1bit) 

- User LED x4 

- Seven segment LED module x1 

- Status LED (Power, Done) 

- Power-on Reset 

- JTAG Connector(7 pin socket) for download cable connection 

- JTAG buffer for stable download or debug 

- 5.0 V single power supply operation (External input or USB Bus power) 

- High quality six layers PCB.(Immersion gold) 

- Compact size 2.087″ x 2.126″ (53 x 54 mm) 

- ESD and Surge protection component for USB I/F 

- Tested all I/O 

- RoHS compliance 

- Made in Japan 

About Xilinx

Xilinx (NASDAQ: XLNX) is the worldwide leader in complete programmable logic solutions. For more information, visit www.xilinx.com.

About HuMANDATA LTD.

HuMANDATA LTD. is a manufacturer of various FPGA/CPLD boards as well as electrical equipment in Japan. Established in July 1990, the company can supply superior products with short lead-time, and can produce various kinds of products in small lots. For more information, please visit www.hdl.co.jp/en.

Xilinx has launched a new set of Targeted Design Platforms (TDP), at the 2102 National Association of Broadcasters (NAB) show in Las Vegas this week. The Display TDP supports development of content for emerging quad High Definition 4K2K (Quad HD) displays. Aaron Behman, Senior Manager for Broadcast & Consumer Market Segments, says that Xilinx worked with alliance partner Tokyo Electron Device Ltd. on the Display TDP, which will be sold under the inrevium brand for $2,995. The Display TDP uses the 28nm Kintex-7 FPGA. Xilinx and TED include three reference designs with the Display TDP, including a mosaic design function which enables users to stitch together four individual 1920×1080 video streams into a single 4K2K display. Other reference designs are provided for performing standard HD to 4K2K up-conversion, and a 4K2K frame rate converter from 60Hz to 120Hz

Xilinx has also updated their Real-Time Video Engine (RTVE) TDP to the Kintex-7 FPGA. The new version adds the capability for dual processing video pipelines, for applications such as picture-in-picture. A new web GUI allows connecting to a LAN router for remote control of the TDP from a tablet, PC or smartphone. Xilinx targets the RTVE at applications in broadcast switchers and routers, multiviewers and display systems.

Xilinx designed a third set of TDPs for Edge Quadrature Amplitude Modulation (QAM) applications, in Hospitality QAM for hotel room Video-on-Demand (VoD), and Converged Cable Access Platforms (CCAP). Designers can add an FPGA Mezzanine Card (FMC) to the TDP, with Digital-Analog Converters (DACs) from Analog Devices (AD9739A) or Maxim Integrated Products (MAX5882). The Edge QAM TDP will be available with the Kintex-7 KC705 Base Board and Kintex-7 K325T FPGA, or the Virtex-7 VC707 Evaluation Board and Virtex-7 485T FPGA. Xilinx is also developing a Quad port version, which will employ dual Virtex-7 X485T/X690T FPGAs.

New solutions to ease programming of FPGAs

The Open Computing Language (OpenCL) is a C-based open standard for parallel programming of heterogeneous multicore systems, which often include a mix of CPUs, GPUs, DSPs, and specialized hardware accelerators. Apple Inc., the original creator of OpenCL, worked with AMD, IBM, Intel, and NVIDIA to submit it as an open, royalty-free standard, to be maintained by the not-for-profit industry consortium Khronos Group in 2008. As Khronos describes it, “OpenCL consists of an API for coordinating parallel computation across heterogeneous processors, and a cross-platform programming language with a well-specified computation environment.”

This description of heterogeneous systems also applies to the new generation of SoC-like architectures that have been introduced by Altera, Xilinx, and Microsemi, with the CPU being one or more ARM cores, and the parallel computational capabilities provided by the programmable FPGA logic. OpenCL offers a possible solution to one of the major hurdles of adopting FPGA SoC devices: the incompatibility of HDL-based FPGA design methodologies used by hardware engineers with the C language programming model used by software engineers. To address this, Altera started a development program in November 2011 to extend the OpenCL standard to FPGA SoCs.

At DESIGN West, Altera demonstrated a methodology for using OpenCL to partition system designs between a host processor and FPGA. To increase system performance, software architects can profile their C/C++ code to identify the portions that would benefit from OpenCL’s ability to transfer execution of multiple parallel instances of “kernel” code to FPGA accelerators. To make the design flow easy to use, FPGA manufacturers must provide OpenCL compilers for their target devices. The OpenCL compiler generates the code needed to drive Electronic System Level (ESL) tools, such as Altera’s Quartus or Xilinx’s AutoESL tools. The ESL tools would, in turn, generate HDL code for gate-level synthesis of the FPGA hardware in the background.

While not yet offering an OpenCL product, Altera has described some successful applications. The company says that goHDR, a manufacturer of High Dynamic Range (HDR) video cameras, was able to port their proprietary video codec to OpenCL while continuing to work entirely in a C language environment. With Altera’s OpenCL-to-ESL flow, goHDR was able to implement an FPGA in less than a week. The companies estimate that design process using a traditional HDL flow would have taken several months.

Hardware-software partitioning enables low-power design

Microsemi’s SmartFusion cSoC integrates a flash-based FPGA fabric with a 100 MHz ARM Cortex-M3 Microcontroller Subsystem (MSS) and programmable analog function blocks. In a paper and presentation at DESIGN West (“Power Aware Hardware/Software Partitioning on a Customizable System-on-Chip (cSoC) Platform”), Mir Sayed Ali, Senior Staff Applications Engineer in Microsemi’s SoC product group, described how hardware-software partitioning in an FPGA SoC can be used to optimize system power dissipation as well as performance.

As in Altera’s OpenCL flow, the Microsemi low-power design methodology requires system engineers to profile their software in order to identify which tasks consume the most energy. Microsemi recommends use of a tool like the IAR Embedded Workbench for ARM, which can estimate the percentage of energy consumed by individual functions in a system’s application code. Higher energy tasks then become candidates for implementation in the cSoC programmable logic cells. Microsemi also provides their SmartPower tool that enables designers to estimate power from simulations of the hardware implementation prior to testing on actual hardware.

This process of hardware-software partitioning is manual and iterative since there is no assurance that a significant power saving can be achieved, especially for tasks which require a high level of bus activity. To aid in the development of low-power designs, Microsemi offers a set of best-practice suggestions for software developers. As an example, Microsemi advises utilizing interrupt-driven functionality, rather than polling by software. They also suggest using on-chip Direct Memory Access (DMA) for bulk data transfer, and keeping the processor in sleep mode during such idle time operations.

Dual-core FPGA SoCs increase options for embedded operating systems

Xilinx’s version of an FPGA SoC, the Zynq-7000 Extensible Processing Platform (EPP), was featured at the company’s DESIGN West exhibit with a dozen different hardware-software demonstrations. A number of the demonstrations addressed another critical software component: the need to support the commercial embedded operating systems that developers use today, if ARM-powered FPGAs are to compete with standalone Microcontrollers (MCUs) and Microprocessors (MPUs).

For many embedded applications, designers will need to employ a Real-Time Operating System (RTOS). At DESIGN West, Xilinx and Wind River announced that the VxWorks RTOS and Wind River Linux would be added to the list of operating systems that are supported on Zynq. With dual ARM Cortex-A9 cores on the Zynq-7000, software architects can apply the VxWorks RTOS in either a Symmetrical Multi-Processing (SMP) or Asymmetrical Multi-Processing (AMP) mode, or as a guest operating system with the WindRiver Hypervisor.

Adeneo Embedded also announced RTOS support for Zynq at DESIGN West, with a Board Support Package (BSP) that enables users to develop applications with the Microsoft Windows Compact 7 operating system. The Adeneo BSP supports SMP mode and the Open Graphic Library (OpenGL) for Embedded Systems (ES1.1) standard. Xilinx also supports the FreeRTOS in AMP mode, with FreeRTOS running on both cores or with FreeRTOS on one core and Linux on the other. Xilinx also supports Android version 2.3 (Gingerbread) on the Zynq platform, with downloadable source files that enable use of the display controller and OpenGL for Embedded Systems (ES 1.1)-based graphics accelerator that is integrated into these devices. The benefit of the FPGA SoC platforms for software developers is that their processor systems should be bootable without the need to configure the FPGA logic. With Linux, Windows, RTOS, and Android available, engineers will have the flexibility to develop a wide variety of embedded applications using the software tools they are already accustomed to.

More embedded cores in FPGA’s future?

With the new generation of embedded ARM-based architectures, FPGAs are following the same path as ASIC SoCs – from single-core to dual-core devices. Will quad cores be next? Or will we see an FPGA version of ARM’s “big.LITTLE” architecture, which combines one core for performance with another, smaller core for power efficiency? If the FPGA vendors succeed in creating efficient hardware-software design methodologies, this could be just the beginning for the evolution of FPGAs into heterogeneous parallel programmable devices.

Oasys Design Systems, a provider of chip design software, today announced it has closed Series B Funding with investments from Intel Capital, Intel’s global investment organization, and Xilinx, a leading provider of programmable platforms. Funding will be used as working capital to expand Oasys’ research and development team, as well as for further expansion of its worldwide support structure.

Chip Synthesis™ is a fundamental shift in how synthesis is applied to the design and implementation of integrated circuits (ICs). Traditional block-level synthesis tools do a poor job of handling chip-level issues. Oasys’ RealTime Designer™ is the first design tool for physical register transfer level (RTL) synthesis of 100-million gate designs and produces better results in a fraction of the time needed by traditional logic synthesis products. It features a unique RTL placement approach that eliminates unending design closure iterations between synthesis and layout.

“Xilinx has licensed Oasys technology and achieved excellent results across a wide range of designs,” says Salil Raje, vice president of Software and IP Product Development at Xilinx. “We have a long-standing and productive working relationship with the Oasys team and we are pleased to extend our support through this investment.”

“Oasys’ technology has the potential to positively impact the design flow for VLSI chip implementation,” adds Shishpal Rawat, director, Business Enabling Programs at Design Technology Solutions Group, Intel. “This is a new way of thinking for next-generation chip design implementation. We are pleased to invest in Oasys.”

“We are excited to have the venture capital arm of the number one semiconductor company and the number one programmable platforms vendor as investors in Oasys,” remarks Paul van Besouw, Oasys’ president and chief executive officer. “With tapeouts at 45- and 28-nanometer process nodes, Realtime Designer is the proven synthesis solution offering substantial runtime and capacity advantages for some of the world’s most complex designs. Intel Capital and Xilinx have given us strategic support, and their investment will enable us to scale commercially and to continue to advance our technology.”

Previously, Oasys announced that several top U.S. semiconductor companies, such as Texas Instruments, Qualcomm and Xilinx, are already using RealTime Designer. In 2011, Oasys enhanced its Chip Synthesis platform by adding design for test (DFT) capabilities and support for chip-level power design, further extending the fast speed and high capacity of RealTime Designer. These additional features completed the fully integrated Chip Synthesis design flow.

About Oasys Design Systems

Oasys Design Systems is a privately funded electronic design automation (EDA) software supplier with a revolutionary new platform called Chip Synthesis™, a fundamental shift in how synthesis is used to design and implement ICs larger than 20-million gates. It has attracted the support of legendary EDA leaders and its RealTime Designer™ product is in use at leading-edge semiconductor and systems companies worldwide. Corporate Headquarters is located at 3250 Olcott Street, Suite 120, Santa Clara, Calif. 95054. Telephone: (408) 855-8531. Facsimile: (408) 855- 8537. Email: info@oasys-ds.com. For more information, visit: www.oasys-ds.com.

Impulse Accelerated Technologies today announced an Arista Networks version of the Impulse C-to-FPGA optimizing compiler, in a kit providing everything needed for Arista users to compile their C algorithms to the FPGA integrated in Arista’s new 7124FX AppSwitch. Impulse C is a C-language development environment for FPGAs that allows software algorithms to be quickly and efficiently implemented in programmable hardware.

The Arista 7124FX AppSwitch is a 24-port 1/10-Gbps switch with hot-swappable redundant power supplies and fans packed into a 1RU box. What makes the 7124FX unique is the FPGA containing 6.2 million gates that are truly field programmable. The 7124FX is targeted at applications that can make use of high-capacity, low-latency logic in FPGAs at the network level, such as high-frequency trading, deep packet inspection, and media transcoding.

Where FPGA programming normally requires hardware design language (HDL) programming skills, the Impulse kit provides a means of compiling C code to the AppSwitch FPGA. In this tool flow, C algorithms can be expressed as streaming processes that are parallelized for acceleration of 10 to 100X, relative to CPU implementations. Impulse C can be used in conjunction with standard C development tools and debuggers, speeding the development and maintenance of algorithms requiring frequent updating.

Impulse C also facilitates the step-by-step validation from hardware-independent C-language to full hardware simulation, through integration with hardware simulators including ModelSim (from Mentor Graphics) or Active-HDL (available from Aldec, Inc.) Impulse C is the most widely accepted tool of this type, with a worldwide user base and over a decade of development.

Arista 7124FX AppSwitch platform support is provided in the Impulse compiler, speeding development time and reducing the need for hardware design expertise. The Impulse C AppSwitch development kit includes reference designs, Altera Quartus synthesis software, necessary drivers and even a programming cable: everything needed to get started programming the 7124FX.

Support from Impulse is available at multiple levels. The standard Impulse C kit for AppSwitch provides examples of “bump in the wire” processing, allowing software developers to more quickly refine their algorithms for FPGA parallelism. Beyond that, Impulse can also offer sample code and consulting to handle various exchange protocols, libraries of analytic functions and full-custom solutions. The 7124FX AppSwitch Development Kit is available through Arista Networks worldwide.

About Impulse

Founded in 2002, Impulse Accelerated Technologies provides software, IP, and training help application developers accelerate their algorithms in FPGA hardware. Impulse C is used worldwide by more design teams than any other C-to-FPGA toolset. Impulse users range from NASA, to Harvard, to Wall Street. www.ImpulseC.com.

HPEC Demo Highlights >95% Data Transfer Efficiency of SRIO in an OpenVPX™ System

ASHBURN, VA – March 13, 2012 – Curtiss-Wright Controls Defense Solutions (CWCDS), a business unit of Curtiss-Wright Controls, has announced that it has successfully demonstrated extremely high data transfer efficiency in an OpenVPX™-based High Performance Embedded Computing (HPEC) system. The demonstration featured the world’s first HPEC 6U VPX subsystem in which Serial RapidIO® (SRIO) data was transmitted between an Intel® 2nd Generation Core® i7 processor, Freescale® 8640 Power® Architecture processor and a Xilinx® Virtex®-6 FPGA, the three leading building blocks of high performance Digital Signal Processing (DSP) embedded systems for defense and aerospace C4ISR applications such as image, signal and radar processing. The demonstration, based on Curtiss-Wright’s rugged COTS OpenVPX board modules, was also the industry’s first to show an Intel CPU running Gen 2 SRIO, an achievement made possible through use of the IDT’s groundbreaking Tsi721 PCIe2-to-SRIO2 RapidIO bridge. Results of the demonstration include data transfers between Intel CPUs rated at 1.7GB/s achieving 95% of the theoretical maximum wire speed for a given physical link into the switch fabric. Furthermore, these results were achieved with a near zero overhead burden on the processor thanks to the high-speed DMA feature of the Tsi721 and SRIO’s inherent guaranteed-by-hardware data transmission.

With support for both Gen1 and Gen2 SRIO and true interoperability between all three of the embedded industry’s most popular processor and FPGA device types, this demonstration highlights the advances that have been made in bringing open standard-based HPEC processing to rugged military embedded systems.

“Gen2 Serial RapidIO is the highest speed fabric available to date for use in OpenVPX™ systems, with speeds up to 20 Gbps. Using the Tsi721 in a x4 configuration at 5 Gbaud, resulting performance was 40% faster than 10 Gigabit Ethernet,” said Lynn Bamford, senior vice president and general manager of Curtiss-Wright Controls Defense Solutions. “We are very excited to be the first COTS system solutions provider to demonstrate the levels of interoperability to make high performance HPEC systems practical and cost-effective. The emergence of COTS-based HPEC processing in compact, rugged deployable subsystems promises to deliver supercomputing performance in SWaP-constrained embedded military applications.”

“We are pleased to deliver the Tsi721 into the embedded computing market, allowing customers to cluster large systems with PCIe enabled processors such as the Intel Core i7 with the 20 Gbps per link performance of RapidIO Gen2 based systems,” said Tom Sparkman, vice president and general manager of the Communications Division at IDT. “With our production RapidIO Gen2 switches and PCIe2-to-SRIO2 bridge, customers such as Curtiss-Wright Controls Defense Solutions are able to provide highly scalable, high bandwidth, low latency multi-processor systems while delivering 95% of available bandwidth into i7 processors. This is achieved with 40% higher performance than Ethernet options and with no protocol termination overhead.”

The SRIO Interoperability Demonstration comprised

* Intel 2nd Generation Core i7 CPU to Intel 2nd Generation Core i7 CPU SRIO data transmission using the IDT Tsi721 PCIe to SRIO bridge 

* Intel 2nd Generation Core i7 CPU to Freescale 8640 SRIO data transmission 

* Intel 2nd Generation Core i7 CPU to Xilinx Virtex6 (with SRIO endpoint IP) FPGA SRIO data transmission 

* Use of IDT CPS1432 Gen2 SRIO switch 

* Use of IDT Tsi578 Gen1 SRIO switch 

* The Intel processors were located on the Curtiss-Wright CHAMP-AV8 dual 2nd Generation Core i7 boards. 

* The 8640 processor and Xilinx Virtex6 FPGA were located on the Curtiss-Wright CHAMP-FX3 FPGA processing engine with FMC I/O expansion. 

All of the SRIO transfers in the demonstration were bi-directional. Interoperation included successful use of three different DMA engines native to each device: Tsi721, 8640 and Xilinx V6.

Curtiss-Wright Continuum HPEC Subsystem Components

The CHAMP-AV8 and CHAMP-FX3 are examples of elements of Curtiss-Wright’s Continuum HPEC initiative. Continuum HPEC systems consist of a large number of distributed processors, IO, and software stacks connected by a low latency system fabric. HPEC capabilities are developed in our Ashburn, VA, HPEC Center of Excellence. With scalable architectures, dataflow modeling and configuration validation, Curtiss-Wright’s Continuum HPEC customers can source embedded supercomputing platforms that integrate Intel®-based multi-processor boards with AVX, GPGPU co-processors, Xilinx® Virtex® 6 FPGAs, SRIO and Ethernet switching with Open Standard software solutions including VxWorks®, and Linux with OpenMPI and OFED software interfaces. Supported products include Curtiss-Wright’s CHAMP-FX3 Virtex6 FPGA board, the CHAMP-AV8 dual 2nd Generation Core® i7-based multiprocessor board, the VPX6-1956 2nd Generation Core i7 SBC, the VPX6-6902 sRIO/Ethernet switch, and the VPX6-490 GPGPU module. OpenVPX™ enclosures are supported including a small 5-6 slot and 19” rack 16-slot air-cooled Chassis.

For price and availability information on CWCDS HPEC solutions, please contact the factory. Click here for more information on the CHAMP-AV8. Click here for more information on the CHAMP-FX3.

Sales & Editorial Contacts

For additional information on CWCDS HPEC solutions please visit: www.cwcdefense.com.

For editorial information regarding Curtiss-Wright Controls Defense Solutions products or services, contact John Wranovics, public relations director, Curtiss-Wright Controls, Tel: (925) 640-6402; email: jwranovics@curtisswright.com.

Sales inquiries: Please forward all Sales and reader service inquiries to Jerri-Lynne Charbonneau, Curtiss-Wright Controls Defense Solutions, Tel: (613) 254-5112; Fax: (613) 599-7777; e-mail: sales@cwcdefense.com. Curtiss-Wright Controls Defense Solutions, Tel: (978) 952-2017.

About Curtiss-Wright Controls Defense Solutions

Curtiss-Wright Controls Defense Solutions (CWCDS) is a long established technology leader in the development of rugged electronic modules and systems for defense applications. CWCDS serves as a technology and integration partner to its customers, providing a full range of advanced, highly engineered solutions from modular open systems approaches to fully custom optimized solutions. Our unmatched capabilities and product breadth span from industry standard based COTS modules to complete electronic subsystems. The company’s modules and systems are currently deployed in a wide range of demanding defense & aerospace applications including C4ISR systems, unmanned subsystems, mission computing, fire control, turret stabilization, and recording & storage solutions. Additionally, the company’s broad engineering capabilities combine systems, software, electrical, and mechanical design expertise with comprehensive program management and a broad range of life-cycle support services. For more information visit www.cwcdefense.com.

About Curtiss-Wright Controls, Inc.

Headquartered in Charlotte, NC, Curtiss-Wright Controls is the Motion Control segment of Curtiss-Wright Corporation. With manufacturing facilities around the world, Curtiss-Wright Controls is a leading technology-based organization providing niche motion control products, subsystems and services internationally for the aerospace and defense markets. For more information, visit www.cwcontrols.com.

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This press release contains forward-looking statements made pursuant to the Safe Harbor provisions of the Private Securities Litigation Reform Act of 1995. Such statements, including statements relating to Curtiss-Wright Controls’ expectations of future performance of this contract, the continued relationship with a customer, the continued success of these military programs and the future opportunities associated with these programs, are not considered historical facts and are considered forward-looking statements under the federal securities laws. Such forward-looking statements are subject to certain risks and uncertainties that could cause actual results to differ materially from those expressed or implied. Readers are cautioned not to place undue reliance on these forward-looking statements, which speak only as of the date hereof. Such risks and uncertainties include, but are not limited to: a reduction in anticipated orders; an economic downturn; changes in competitive marketplace and/or customer requirements; a change in US and Foreign government spending; an inability to perform customer contracts at anticipated cost levels; and other factors that generally affect the business of aerospace, defense contracting, marine, electronics and industrial companies. Please refer to the Company’s current SEC filings under the Securities Exchange Act of 1934, as amended, for further information.

Osaka, Mar 12, 2012 – HuMANDATA LTD., a manufacturer of various FPGA/CPLD boards in Japan, today released AP68-04, a new stamp size PLCC FPGA module powered by Altera Corp.’s Cyclone III FPGA (EP3C25U256C8N).

HuMANDATA’s AP68-04 comes in compact 25.3 x 25.3mm board that is so compact it can be equipped on universal boards by using a 68-pin DIP IC socket. The AP68-04 operates with only 3.3V power supply and has an on-board 1.2V and 2.5V regulators.

The AP68-04 PLCC FPGA module provides 50 user I/Os, which are divided into two Vccio groups, an on-board 50MHz oscillator, two user LEDs, one user switch, a Power-on Reset IC, and a configuration device.

HuMANDATA’s AP68-04-25 is compliant with the RoHS Directive, and is designed for lead-free soldering.

For the high resolution image, please click here: www.hdl.co.jp/press/2012/12C0069.jpg.

For the full press release, please visit: www.hdl.co.jp/en/index.php?id=213.

For more information, please visit www.hdl.co.jp/en/index.php?id=206.

Specifications:

- Altera CyconeIII (EP3C25U256C8N) 

- Configuration device (Altera: EPCS16) 

- 50 user I/Os 

- Separable Vccio (VIO(A) and VIO(B)) 

- On-board Oscillator, 50MHz 

- User LED (Red x2) 

- User Switch (Slide x1) 

- 3.3V single power supply operation with on-board 1.2V/2.5V regulators 

- High quality eight layers PCB (Immersion gold) 

- Compact 68pin PLCC size (25.3 x 25.3mm) 

- Tested all I/O 

- RoHS compliance 

- Made in Japan 

About HuMANDATA LTD.

HuMANDATA LTD. is a manufacturer of various FPGA/CPLD boards as well as electrical equipment in Japan. Established in July 1990, the company can supply superior products with short lead-time, and can produce various kinds of products in small lots. For more information, please visit www.hdl.co.jp/en .

About Altera Corp.

Altera Corp. (NASDAQ: ALTR) is the pioneer of programmable logic solutions, enabling system and semiconductor companies to rapidly and cost effectively innovate, differentiate, and win in their markets. Altera offers FPGAs, SoC FPGAs, CPLDs, and ASICs in combination with software tools, intellectual property, embedded processors and customer support to provide high-value programmable solutions to over 13,000 customers worldwide. Founded in 1983, Altera is headquartered in San Jose, California, and employs approximately 2,600 people in 19 countries. For more information, please visit www.altera.com.

Contact:

HuMANDATA LTD.

Tel: +81-72-620-2002 (Japanese)

Fax: +81-72-620-2003 (Japanese/English)

URL: www.hdl.co.jp/en/

Editor’s note: While many embedded design considerations depend on the target application, some requirements are inevitable: greater performance, lower costs, and increasingly faster time to market. Thanks to major advancements in process technology, FPGAs address all of these design needs by offering substantial parallel processing capabilities, as well as quick-fix infield upgradability. For a comprehensive overview of how FPGA technology can help achieve embedded design goals, we interviewed executives from the leading FPGA companies and collected excerpts from their responses in this virtual panel discussion.

Figure 1: Executive panelists (click graphic to zoom)

ECD: With higher power requirements and recurring costs than custom logic or ASICs, which projects are best suited for FPGA technology?

BURICH: FPGAs have benefited significantly from Moore’s Law, and as a result have been able to stay at the bleeding edge of process technology while at the same time considerably reducing power consumption and development costs. As the costs of advanced process technologies rise (about $60 million for an ASIC at 40 nm), it gets harder to justify the upfront R&D costs. Today, we see a shrinking number of applications that can justify a leading-edge ASIC – mostly restricted to cell phones, PDAs, video games, and other high-volume applications. Those who can’t justify such an upfront investment seek to use trailing-edge process technologies.

In contrast, FPGAs can afford to use the latest process node and take advantage of Moore’s Law because there is a much wider array of applications that FPGAs can target. Today’s leading-edge FPGAs are 2-3 process nodes ahead of where most ASICs are, giving users the most advanced process technology available plus all the accompanying benefits at an overall lower cost. Development costs of leading-edge FPGAs are dramatically reduced because FPGA vendors can aggregate development costs across thousands of designs and customers. FPGAs are ideally suited for industrial, communications, automotive, military, medical, aerospace, and other designs with sub 1 million volumes or where a high degree of flexibility is required.

GETMAN: You have to be careful not to take an overly simplistic view when looking at power and cost and comparing different components like ASICs, ASSPs, FPGAs, and new hybrid products like Extensible Processing Platforms (EPPs). The comparison cannot just be at the device level; it also requires analysis at the system level and overall project level.

Design engineers must first answer some tough questions concerning costs, tool availability and effectiveness, production volume, time to market, and how best to present this information to management to gain support throughout the design process.

It’s interesting to compare these technologies, but in the end, the application is the final differentiator. A list of design objectives in order of importance, including cost (both development – nonrecurring engineering, and production – recurring unit cost), die size, time to market, tools, performance, and IP requirements must first be created. Then ask which technology best meets those objectives.

That analysis cannot just stay at the device level, where ASSPs and ASICs have an advantage with regard to both power and cost. For ASICs, the upfront cost means that only very high-volume applications can efficiently use an ASIC. Another trend is for companies to develop “kitchen sink ASICs,” where the design requirements for many different end products are the same, thus a single ASIC targeting multiple applications can be developed. However, this creates a problem with design complexity and project risks. Therefore, many customers are moving away from this approach after experiencing product delays and receiving products that, in the end, do not serve anyone’s needs perfectly. The other disadvantages that kitchen sink ASICs bring are that the silicon area is “inflated” to accommodate all the target applications, and therefore is less cost- and power-efficient.

We have always told our customers that if you have an ASSP that does exactly what you want and do not need or want to differentiate your product through hardware functions, then maybe that ASSP is the right choice for you. Most designs, however, can benefit from a flexible, programmable device that targets their unique applications and differentiates their products from the competition.

To accomplish that, many ASSP users add an FPGA next to their ASSP. While this offers a certain level of flexibility, it can also present some performance and power consumption challenges, stemming from the interface between the ASSP and the FPGA. This is why in the past few years, we have seen a push for fully integrated FPGA solutions, as well as FPGA vendors starting to offer hybrid solutions like an EPP (see Figure 2).

Figure 2: An Extensible Processing Platform (EPP) combines a high-performance dual-core ARM processor with standard peripherals and programmable logic. (click graphic to zoom by 1.8x)

Over time, FPGAs have begun taking commonly used blocks such as DSP multipliers, small block RAM memories, and even high-speed serial I/O to offer the best balance of features and flexibility. The Zynq-7000 EPP family uses standard ASIC techniques to harden close to 11 million ASIC gates in the processing subsystem. This type of architecture swings the financial and technical bar around total cost of ownership, performance, and power radically away from traditional ASICs.

Massive parallel processing capabilities are another key benefit of FPGA technology, allowing designers to reach a level of performance not achievable with ASSP products. Additionally, using FPGAs within an EPP greatly reduces the risks involved when designing with ASICSs and ASSPs, as these devices cannot accommodate late design changes and do not provide the flexibility of infield upgrades. FPGAs offer the ultimate system integration platform to meet the growing need for programmable systems that cut development cycles, enable adoption to changing standards, and extend product lifetimes through field upgradability.

This segues perfectly to reducing time to market, a major advantage for any company’s product. FPGA technology allows our customers to move to market quickly, often in a matter of weeks, while drastically reducing their R&D costs. We offer design engineers a blank device that can be configured and reconfigured on-the-fly to implement any logic function that can be performed by an application-specific device. FPGA technology allows our customers to make changes to their designs very late in the design cycle. Even after the end product has been completed and shipped, they can extend its useful life by reprogramming the FPGA.

Innovations in FPGA technology have reduced the gap of power per device, making FPGAs much more competitive from a power standpoint. The battle to deliver maximum performance with minimum power expenditure is center stage in the evolution of the FPGA. Power conservation affects every budget, whether technological or financial. Product acceptability, reliability, and profitability depend as much or more on power efficiency as they do on performance, regardless of the type of project.

However, the key element of power savings will come from integration and reduced power consumption due to the chip-to-chip interface, which again, must be analyzed at the system level and not just at the chip level.

Increased system performance means new process technologies, massive parallel processing capability, advances in memory interfaces, high-speed transceivers (up to 28 Gbps), and no bottlenecks due to chip-to-chip interfaces. Decreasing power again relates to process technology, and in our case, this means using TSMC’s high-performance, low-power 28 nm process (a unified architecture across all of our 7 series FPGAs), other technology innovations, and burning no power to do chip-to-chip interfaces in a single device, as well as using fewer power supplies to reduce power consumption on the boards. Cost reduction is based on the use of a single device, which means there are no upfront costs and fewer components used on the board, resulting in a smaller bill of materials and a simpler design.

RILEY: The traditional trade-offs between FPGAs and ASICs/custom devices are still in effect. For a specific application, ASICs are lower power and lower cost, but they take much longer to develop and require a large upfront investment. What’s changing are the time-to-market requirements and useful market life for many projects.

Communications and wireless infrastructure developments are under tremendous pressure to get to market, driving engineers to consider process technologies that are reprogrammable and available today. In many cases, this is an FPGA. In the past few years, companies such as Lattice Semiconductor and SiliconBlue Technologies have been developing FPGAs that have solid capabilities and are priced well under $1. In fast-moving, cost-sensitive markets like consumer mobile, this type of solution is often the only way to add functionality in such a short time.

ECD: How can FPGA technology help embedded design teams deal with reduced budgets and increased system complexity?

GETMAN: While system complexity increases and the reduction of system design budgets becomes more of a reality, embedded system designers are jumping on the FPGA technology bandwagon to shorten design cycles, battle obsolescence, and simplify product updates. Using the constantly growing number of integrated FPGA development tools, reusable logic elements, and off-the-shelf modules, designers are creating new and innovative embedded systems that can be easily reconfigured for updates and changes in requirements with only a minimum impact on engineering and manufacturing.

FPGA designs combine multiple components into a single package that reduces component count, board size, and manufacturing complexity. Processors, memory, custom logic, and many of the peripherals in a typical embedded project are now in the FPGA. Today’s FPGA architecture has grown into billions of logic blocks (equivalent to gates), and with programmable interconnection flexibility designers can easily create hardware functions that exactly match the needs of a specific embedded application.

Drop-in IP cores from device vendors, third-party suppliers, and the open-source community ease FPGA set-up. The standardization of an IP interface (we use the AMBA 4 AXI standard) also greatly reduces design complexity when integrating functions into a single device. Furthermore, fueling a comprehensive ecosystem of hardware design tools, as well as software design tools and operating systems, is yet another key element of reducing design complexity.

Designers can segment FPGA-based signal processing algorithms into parallel computing structures to boost performance. High-level synthesis tools such as AutoESL can help simplify FPGA design and enable companies and developers not familiar with FPGAs or even hardware design to reap the inherent benefits of FPGA technology.

By utilizing a broad set of tools, the embedded designer’s tool bag for enabling FPGA technology has become increasingly mainstream. FPGA vendors are putting significant time and money into their development tools to improve the turnaround time, which will permit more iterations while reducing time to market and saving engineering efforts. The integration of many system elements into a single device reduces design complexity, as there are fewer chip-to-chip interfaces, as well as fewer performance bottlenecks.

RILEY: FPGAs are often used as bridging or coprocessing solutions. This allows embedded engineers to build systems out of the products they have. Can’t connect two dissimilar processors? No problem. FPGAs support a wide range of I/O types. Can’t handle the processing load? No problem. FPGAs can be configured to offload key functions.

FPGAs help get system products to market quickly, and the price and power of FPGA solutions has been dropping at a breakneck pace the past 10 years. FPGAs are used today in smart phones, tablets, laptops, handheld GPS devices, and many other platforms that were once the sole domain of custom logic.

BURICH: Designers today are challenged to get many different systems to market in shorter and shorter periods of time. By enabling easy customization for different features, price points, and evolving standards, FPGAs enable engineers to design a common platform and quickly spin off varying systems.

One of the most disruptive aspects of embedded design is adopting a new architecture to meet changing requirements. The industrial, medical, and military segments, for example, are also very concerned about product longevity and avoiding device obsolescence. By designing with FPGAs, customers can make incremental changes to a common design to adapt to changing market needs or industry specifications. Having a common tool flow with extensive design reuse addresses budget and time constraints.

New System-on-Chip (SoC) FPGAs featuring hard ARM processor subsystems also help embedded design teams address reduced budgets (see Figure 3). Today’s leading-edge FPGAs are targeting 28 nm process technology, which relatively few commercial CPUs or ASSPs use. A monolithic SoC FPGA system maximizes power efficiency and software partitioning flexibility. SoC FPGAs allow hundreds of data signals to connect different functional areas, thus enabling 100 Gbps or greater bandwidth with nanosecond-level latencies, representing orders of magnitude better performance and latency than discrete implementations. Furthermore, monolithic integration permits memory controllers to be shared, allowing high-bandwidth memory access for hardware accelerators. A monolithic SoC FPGA implementation enables embedded design teams to increase system performance while lowering system costs and reducing power versus a two-chip solution.

Figure 3: Today’s SoC FPGAs combine a hard ARM processor subsystem with the fabric of a 28 nm FPGA. (click graphic to zoom by 1.9x)

ECD: One of the biggest obstacles to adopting FPGA technology has been the steep learning curve associated with development tools. How has this changed?

BURICH: This depends on the designer’s background. Those familiar with ASICs can quickly adapt to FPGA design flows and save time through the benefits of quicker verification in real silicon. Those who are not familiar with Real-Time Logic (RTL) will have a steeper learning curve. This is being addressed in two areas. The first is system-level design tools such as Altera’s Qsys, which enables designers to quickly assemble different design blocks using a higher-level graphic block environment. The second is automated RTL development from C language source. While this approach has been tried for many years, it is now coming of age for embedded developers with standards such as OpenCL. OpenCL also addresses the increasing challenge of designing multicore systems. Altera recently announced a program for evaluating FPGA-based OpenCL implementations.

GETMAN: Developing FPGA solutions can be complex, requiring the appropriate software tools. While each chip technology requires specific design tools, FPGA users are shielded from concerns of manufacturing yield and submicron issues by the nature of FPGA design flow, which brings ease-of-use, cost, and time-to-market benefits. FPGAs arrive fully tested and physically functional; the FPGA supplier handles physical design, verification, and characterization. Xilinx offers integrated design and debug tools for logic, DSP, and embedded processing, plus interfaces to third-party tools. FPGA design tools have improved dramatically, particularly [those] tools that apply high-level languages or interfaces to develop applications, such as MATLAB/Simulink from MathWorks.

Depending on the provider, software to program FPGAs varies in content and value-add features like compilation and editing tools. Very high-speed Hardware Description Language (VHDL) is the most common development language used. It allows FPGAs to be programmed via an easy-to-use graphical development environment. Additionally, FPGA vendors who provide tools such as development boards, support, and reference designs simplify the FPGA design process.

Conversely, there are longer design and verification cycles for ASICs, with a high likelihood of design re-spins and associated penalties. Plus, costly verification tools, training, and resources are required.

FPGA vendors who continue investing in software development tools and IP will enable more complex systems to be designed while carrying their silicon platform forward and promoting growth. The challenges going forward have not changed. These challenges continue to be reducing power, providing more capability at a lower cost, and further simplifying the programming. As progress is made on all of these fronts, the market share for FPGAs is increasing over ASIC/ASSP providers.

RILEY: The learning curve for FPGA design tools depends on where you are coming from. If you are an ASIC designer, the FPGA design tools will seem familiar. A design flow that includes HDL design entry, simulation, synthesis, and place and route is similar to an ASIC flow. For a software engineer who is used to programming in C/C++, the FPGA design flow will be new and require a learning curve.

Some vendors have claimed that you can write your code in C and their tools will automatically convert it to HDL. In my experience, this process still requires much human engineering to achieve the system throughput goal that drove the need to move beyond the confines of the microprocessor. There are well-established methodologies for partitioning a design between software and dedicated hardware. These still result in the best cost and performance, and FPGAs allow designers to experiment with different partitioning. Over the years, some FPGAs have included integrated processors, but they have not been successful. One reason for this is the lack of flexibility.

The world of microprocessors is vast. You can find any price, performance, or power point you desire from multiple vendors. Once you integrate the processor into the FPGA, your options become limited very quickly.

ECD: What types of IP core libraries do you offer to shorten the embedded design process?

RILEY: Lattice offers a wide range of IP cores, reference designs, and evaluation boards for PCI Express, Serial Rapid I/O, XAUI, Finite Impulse Response (FIR) filtering, Fast Fourier Transforms (FFTs), image and video scaling, MIPI interfaces, and more. Lattice focuses on the mid-range and low-density segments within the FPGA market. This means we concentrate on delivering high-end capabilities such as DDR3 memory interfaces and advanced filtering in low-cost, low-power FPGA platforms.

Lattice offers IP cores through a novel tool called IPExpress, which allows customers to change high-level parameters and generate new IP structures tuned to their feature, size, and performance requirements. Lattice provides many reference designs for free at our website. We also work closely with our customers to generate custom designs to meet their needs.

BURICH: IP libraries are important, and we offer a wide range of cores from memory controllers to embedded peripherals to high-speed communications interfaces. One of the most popular is our Video and Image Processing (VIP) Suite and our Nios II embedded processor IP. We also have a partner ecosystem that offers IP cores tailored to meet specific application requirements.

Just as important as the IP offering is the interconnect logic that ties the IP cores together into a coherent system. Altera offers a system integration tool (SOPC Builder) that automatically generates the logic that handles seemingly trivial yet critically important tasks of bus width adaptation, bus arbitration, bursting, interrupts, and more. We connect memory-mapped and streaming interfaces seamlessly and support high-performance bus standards like ARM AXI, as well as our lightweight, open Avalon interface standards. With the introduction of Qsys, we now generate a Network-on-Chip architecture offering even higher levels of performance and flexibility. Designers can not only assemble IP cores into a custom system, they can also create custom subsystems that can be shared internally to exploit the FPGA design reuse advantage.

GETMAN: Xilinx offers nearly 100 different embedded processing peripheral IP cores in categories including Processor IP Cores, Interface/Bus/Bridge IP, Peripheral IP, Communications IP, Infrastructure IP, Memory Controller IP, and Debug IP. These cores are included with the ISE Design Suite: Embedded Edition Development Kit and work directly in our Platform Studio, which supports MicroBlaze and PowerPC for PLB-based cores and MicroBlaze for AXI-based cores.

ECD: Which industry standards do you support to provide customers off-the-shelf, reconfigurable designs?

GETMAN: We see two aspects with regard to supporting industry standards, one at the external level and one at the internal level. At the external level, take the FPGA Mezzanine Card (FMC) defined in VITA 57 as an example. By using the reconfigurable I/O of FPGAs, design engineers can easily change a transceiver protocol or an I/O standard and route it through a different card connected to the FMC connector on our boards to create a new application/customer. Examples of internal standards that enable quick configuration/reconfiguration are AMBA 4 AXI, IP-XACT, and the proposed IEEE standard for IP Quality (QIP).

We support many interface standards for most market segments, including wireless communications, aerospace and defense, intelligent video, automotive, instrumentation, and medical imaging, which eases the connection to other systems. Having a comprehensive IP offering from Xilinx and its partners enables designers to quickly reconfigure their designs for applications or products.

RILEY: Lattice supports a wide range of hardware standards to help customers evaluate our silicon, design tools, and IP cores. Many of these evaluation boards are available for under $199, which allows customers of all sizes to experiment with Lattice products. Two standards that are popular with embedded designers are PCI Express and the Advanced Mezzanine Card. The AMC provides an FMC expansion connector, a USB-B connection to UART for runtime control, an RJ-45 interface to 10/100/1000 Ethernet, and an SFP transceiver module cage and connection.

BURICH: From the IP interconnect perspective, we support ARM’s AMBA AXI bus standard, as well as our own open Avalon bus standards (memory-mapped and streaming). Our Qsys system integration tool supports both AXI and Avalon, and the architecture of the tool is such that we can add other interconnect standards easily as needed.

From the IP interface standard perspective, we and our partners offer a wide range of IP cores that can be assembled into a custom system quickly with Qsys. Altera offers a wide variety of IP blocks of differing size and complexity, from the basic arithmetic blocks to transceivers, memory controllers, microprocessors, signal processing, and protocol interfaces. Altera and its third-party IP partners offer a broad portfolio of off-the-shelf, configurable IP cores optimized for Altera devices. Licensed and unlicensed IP is delivered and installed with our Quartus II design software.

ECD: Marketing materials for new processors with Advanced Vector Extensions (AVX) suggest replacing external FPGAs with code. Will this new architecture affect the FPGA industry?

RILEY: AVX is an extension of the x86 instruction set targeted at improving performance, specifically in floating-point designs. Processors with AVX can work together with FPGAs to handle tasks such as bridging a dual-sensor interface to a new processor (see Figure 4). These extensions will allow embedded designers to do more with their x86 architectures; however, the performance gulf between a processor and an FPGA is still very large. Benchmark applications such as Finite Impulse Response (FIR) filtering, Fast Fourier Transforms (FFTs), and 2D image filtering are still many times faster on FPGAs than microprocessors. Also, FPGAs are superior for implementing general-purpose logic and bridging to dissimilar devices. So AVX will be a big help to many embedded designers, but it won’t obviate the need for FPGAs in embedded designs.

Figure 4: Lattice Semiconductor’s MachXO2 FPGA can be implemented as a high-speed CMOS sensor interface. (click graphic to zoom by 1.9x)

BURICH: Custom hardware has always outperformed software. The trade-offs of off-the-shelf hardware extensions are:

1. They might not be optimal for a broad range of applications; only custom, application-specific hardware can deliver the best performance. AVX offers benefits to the PC and tablet industries, but FPGAs already come with strong parallel processing capabilities and are the better fit for embedded markets. One-size-fits-all acceleration incurs the cost of answering a wide range of needs, resulting in inherent inefficiencies.

Off-the-shelf hardware extensions don’t lend themselves to establishing a competitive advantage because competitors have access to the very same hardware and software. Custom hardware can create a competitive differentiator and help developers create a product that outperforms the competition in both performance and revenue generation.

GETMAN: These types of specialized extensions are not new trends to the industry. As an example, MMX was introduced in the mid ’90s on Intel Pentium processors to improve multimedia processing. The ARM architecture is also enhanced with NEON extensions that serve a similar purpose.

In a design where an FPGA is used to perform simple accelerator functions for the main processor, the extra gain in performance from AVX will remove the need for some FPGAs. However, FPGAs are used for other functions beyond just simple accelerators, such as adding peripherals to the main processor, and the AVX architecture cannot address this need covered by FPGAs.

With the continual need for increased system performance, fixed defined instructions might not perfectly address a great deal of proprietary algorithm processing. This results in more clock cycles per function, yielding not only lower performance, but also higher power. This makes the massive parallel approach provided by FPGA architecture well-suited for hardware acceleration, thus enabling customers to continue achieving higher system performance. Therefore, the answer on industry effect is both yes and no.

In addition, FPGA companies have introduced new hybrid architectures (such as the Zynq-7000) that combine application-class processors and programmable logic. These new architectures offer the capability to add hardware accelerators in the programmable logic and have it controlled by the processor in a similar way as AVX. The massive parallel processing capabilities of programmable logic available in these hybrid devices enable performance beyond what AVX instructions could bring to a processor.

Misha Burich is the senior VP of R&D at Altera.

Lawrence Getman is the VP of Processing Platforms at Xilinx. Prior to this role, Lawrence was in charge of corporate development at Xilinx. Before joining Xilinx, he worked as the VP of Business Development at Triscend Corporation and held a variety of marketing and sales roles. Lawrence has a BSEE from Rochester Institute of Technology and an MBA from San Jose State University.

Sean Riley is Corporate VP of the Infrastructure Business Group at Lattice Semiconductor.

Altera
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www.altera.com

Xilinx
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Lattice Semiconductor
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www.latticesemi.com

Lattice Semiconductor Corporation today announced it will exhibit at Mobile World Congress, Feb 27th – March 1st at Fira de Barcelona in Barcelona, Spain. Lattice will be located in Hall 2.1, Stand 2.1A56, and will be featuring the company’s mobileFPGA™ platforms including the new iCE40™ and MachXO2™ FPGAs and ispMACH® 4000ZE CPLDs.

More than 20 mobile products, where Lattice mobileFPGA devices enabled product designers to rapidly add differentiating features to their products, will be displayed. The company will also give demonstrations including a video camera-to-LVDS display bridge that supports 1366 x 768 pixels and 525 Mb/s transfer rates in a low cost mobileFPGA device. “Over the last two years Lattice has demonstrated the need for and viability of mobileFPGA devices” said Gordon Hands, director of marketing at Lattice Semiconductor. “Mobile World Congress” represents a great opportunity for us to further engage the ecosystem by demonstrating how to enable rapid innovation at a low cost.”

With a combination of small form factor (as small as 2.5 x 2.5mm), low power (as low as 18uW standby power) and high-volume pricing (starting below $1.00 per unit), Lattice programmable devices enable customers to easily differentiate products while dramatically decreasing time to market for mobile devices where extended battery life and portability are required. Products incorporating Lattice mobileFPGA devices include: smart phones, tablets, e-readers, digital cameras and personal navigation devices. In system programmability allows manufacturers of these products to make design changes without significant circuit board modifications.

The Company’s extensive library of more than 40 IP cores, including multiple memory controller, display, connectivity, and sensor management IP cores, together with development kits, reference designs, and state of the art development tools, help designers decrease development time, supporting instant innovation.

The IC-FEP-VPX3b is ideal for applications such as radar, sonar, electronic warfare, imaging and communications, by offering high performance logic and powerful Digital signal processing slice resources, while maintaining low power.

The FMC site, being VITA 57.1 compliant, interconnects ADC, DAC, general IOs, video, Serial FPDP cards, or additional FPGA FMC modules.

In terms of processing unit, the board, based on a Xilinx Virtex-6 FPGA, offers two banks of 40-bit 1.25 GB DDR3 memory, and a Spartan-6 control node. Complying with the VPX standard, the IC-FEP-VPX3b, features four 4-lane fabric ports on the P1 and general purpose IOs (on P2).

Available in standard, rugged and conduction-cooled grades, the IC-FEP-VPX3b comes with the Xilinx ISE design tool

The IC-FEP-VPX3b enriches the extended comprehensive range of Interface Concept open VPX boards among which, SBC, Ethernet and PCIe switch, Graphic and storage modules.

(www.interfaceconcept.com/index.php?rub=vpx_prod[...]).

NORWOOD, Mass. — Analog Devices, Inc. (ADI), the leading provider of data conversion technology*, today introduced two data converter FMC boards (FPGA mezzanine cards) that connect to Xilinx Inc.’s new 28nm 7 series FPGA (field programmable gate array) evaluation kits. ADI’s high-speed AD9739A D/A converter and AD9467 A/D converter FMC boards support multiple generations of Xilinx kits — including the company’s new Kintex-7 FPGA evaluation kits Xilinx announced today. The new Analog Devices FMC boards include all of the HDL (hardware description language) code and device drivers needed for designers to engage in rapid prototyping and reduce development time and risk. Both products are being demonstrated at the DesignCon 2012 trade show in Santa Clara, Calif., in the Xilinx booth (#732).

“The availability of low cost commercial off the shelf hardware, such as the AD9739A FMC board, and the new Kintex-7 development boards, allows our customers to quickly prototype and evaluate many of the IP Cores which we offer,” said Jean-Claude Basset, technical director/manager, MVD Cores**, a Certified Member of the Xilinx Alliance Program. “We have verified our digital RF up converter IP cores with the AD9739A FMC board and Xilinx’s Virtex-6, Kintex-7 and Spartan-6 boards and recommend that our customers use this hardware to evaluate our IP Cores.”

For information about ADI’s FMC boards: www.analog.com/Xilinx

To order ADI’s FMC boards***:

AD9739A FMC: www.digilentinc.com/AD9739A-FMC

AD9467 FMC: www.digilentinc.com/AD9467-FMC

Get support at ADI’s EngineerZone™ online technical support community: ez.analog.com/community/fpga

To learn more about ADI’s data conversion technology: www.analog.com/en/data-converters/products/inde[...]

“ADI’s new FMC boards, integration software and industry-leading data conversion expertise help engineers designing with Xilinx’s Kintex-7 series FPGAs to move more quickly through system prototyping and get their products to market faster,” said Dave Babicz, director of Global Alliances, Analog Devices. “At the same time, our new boards are backward compatible with other Xilinx FPGAs, which means that engineers will be able to design products that meet a range of performance criteria using a simplified design environment.”

“Xilinx’s Targeted Design Platforms accelerate system development and integration by providing the industry’s most comprehensive development kits, which include boards, tools, IP cores, reference designs and FMC support,” said Raj Seelam, senior marketing manager, Targeted Design Platforms, Xilinx. “Our adoption and support for open standards such as FMC and the AMBA®4 AXI IP core interface strengthens the ability of Xilinx Alliance Program members like Analog Devices to deliver key technologies that make it easier for FPGA users to complete their projects.”

More About ADI’s AD9739A D/A Converter FMC Board

ADI’s AD9739A FMC board is based on the AD9739A, a 14-bit D/A converter that enables cable television and broadband operators to synthesize the entire cable spectrum up to 1 GHz into a single RF (radio frequency) port, while consuming a maximum of 1.1 W of power. The AD9739A 14-bit, 2.5-GSPS D/A converter’s wide bandwidth and dynamic range enable cable operators to increase the QAM (quadrature amplitude modulation) channel densities by 20 times over the densities found in today’s cable modems. Competing D/A converter solutions require an additional 28 LVDS (low-voltage differential signaling) pairs for the data interface.

More About ADI’s AD9467 A/D Converter FMC Board

ADI’s AD9467 FMC board is based on the AD9467, which is a 16-bit, 250-MSPS A/D converter that operates on 35 percent less power at a 25 percent higher sampling rate than any other 16-bit data converter. The AD9467 provides a new level of signal processing performance for test and measurement instrumentation, defense electronics and communications applications where high resolution over a wide bandwidth is needed.

The AD9467 delivers resolution and a fast sample rate while simultaneously achieving a high SFDR (spurious-free dynamic range) of up to 100 dBFS and SNR (signal-to-noise ratio) performance of 76.4 dBFS. The device’s SFDR of 90 dBFS up to 300 MHz analog input and 60-femtosecond rms (root mean square) jitter help lower the signal chain bill of materials component count by allowing engineers to increase system performance at higher intermediate frequencies, thereby reducing the number of signal down-conversion stages.

Availability and Pricing

Product Availability Price

AD9739A FMC board with 14-bit D/A converter

Now

$349

AD9467 FMC board with 16-bit A/D converter

March 2012

Contact Digilent Inc.

About Analog Devices

Innovation, performance, and excellence are the cultural pillars on which Analog Devices has built one of the longest standing, highest growth companies within the technology sector. Acknowledged industry-wide as the world leader in data-conversion and signal-conditioning technologies, Analog Devices serves over 60,000 customers, representing virtually all types of electronic equipment. Analog Devices is headquartered in Norwood, Massachusetts, with design and manufacturing facilities throughout the world. Analog Devices’ common stock is listed on the New York Stock Exchange under the ticker “ADI” and is included in the S&P 500 Index. www.analog.com

This PICMG AMC.0 R2.0 compliant AMC offers a unique combination of features that makes it ideal for telecommunications, defense, and networking applications:

Xilinx Virtex-6 FPGA provides high-performance processing resources with a wide range of devices including logic-oriented LXT and DSP-oriented SXT.

High-speed backplane communications enabled by two 1Gb Ethernet links and up to four x4 GTX fat pipe interfaces.

IPMI backplane interface directly connects to an on-board Pigeon Point MMC with integrated IPMI v1.5 capability.

A comprehensive suite of software and FPGA IP cores including an integrated Xilinx Microblaze processor core and 1 Gb Ethernet and x4 Gen2 PCIe links. The Microblaze processor core provides a Petalogix Linux OS that is ready to use for application control and management.

For additional information, please visit www.nallatech.com/amc-420

SANTA CLARA, Calif.–MoSys, Inc. (NASDAQ: MOSY):

Who:

MoSys (NASDAQ: MOSY), a provider of serial chip-to-chip communications solutions that deliver unparalleled bandwidth performance for next generation networking systems and advanced system-on-chip (SoC) designs, is exhibiting at DesignCon 2012 in booth 615. MoSys will demonstrate interoperability between its Bandwidth Engine® IC and the newest 28nm FPGAs from both Altera Corporation and Xilinx, Inc.

What:

DesignCon is renowned as being the premier event for the semiconductor and electronic design engineering community. DesignCon 2012 is no exception. It is the largest meeting of board designers and is the only event to address chip design engineers’ chip/system/package challenges. It is the place for this community to network, identify solutions to immediate design challenges, and meet in person the solution providers for your next project. DesignCon brings together engineers, suppliers, analysts and media from across the globe, including Asia and the Pacific Rim. DesignCon’s exhibit floor offers the semiconductor and electronic design engineering communities a place to showcase their latest technological advancements and product developments.

When:

DesignCon 2012 begins January 30, 2012 and concludes February 2, 2012. The exhibition takes place on January 31 and February 1, 2012.

Where:

5001 Great America Parkway

Santa Clara, CA 95054

About MoSys, Inc.

MoSys, Inc. (NASDAQ: MOSY) is a provider of high-performance networking memory solutions and high-speed, multi-protocol serial interface intellectual property (SerDes IP). MoSys’ leading edge Bandwidth Engine® ICs combine the company’s patented 1T-SRAM® high-density memory with its SerDes IP and are initially targeted at providing breakthroughs in bandwidth and access performance in next generation networking systems. MoSys’ SerDes IP and DDR3 PHYs support a wide range of data rates across a variety of standards, while its 1T-SRAM memory cores provide a combination of high-density, low-power consumption, high-speed and low cost advantages for high-performance applications. MoSys is headquartered in Santa Clara, California. More information is available on MoSys’ website at www.mosys.com.