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	<title>Multicore &#187; Blog</title>
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	<description>Ever-smaller silicon geometries are reaching their physical limits. This threatens to slow the pace of Moore’s Law to a stand-still. As a result, multicore technology is becoming widely available to address the performance bottleneck. The key to successful multicore product development is system and application level software that takes full advantage of the parallel processing environment without being too difficult or time consuming to write and validate. Multicore silicon allows the flexibility to partition cores for specific functions thereby requiring fewer silicon components or replicating the same processing function across multiple cores to substantially increase processing power. LAN/WAN/MAN networking, mobile 4G/LTE, medical, automotive, and industrial control markets already use multicore processing, and the list is growing. The multicore channel keeps your finger on the pulse of silicon, platform, and software developments as they happen in order to make effective and efficient use of this quickly advancing technology.</description>
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		<title>Multicore TechChannel&#8217;s Facebook Wall 2012-03-27 19:35:21</title>
		<link>http://www.facebook.com/MulticoreTech/posts/343329359036663</link>
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		<pubDate>Wed, 28 Mar 2012 02:35:21 +0000</pubDate>
		<dc:creator>Multicore TechChannel</dc:creator>
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		<description><![CDATA[OpenSystems Media ESC/DesignWest 2012 Booth #2331www.youtube.comOpenSystems Media Booth #2331 at DesignWest 2012]]></description>
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		<title>Facebook Syndication Error</title>
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		<pubDate>Mon, 19 Mar 2012 03:06:56 +0000</pubDate>
		<dc:creator>Facebook.com</dc:creator>
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		<title>Insight from NEI on transitioning to Sandy Bridge. http://www.linkedin.com/news?&#8230;</title>
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		<pubDate>Mon, 20 Feb 2012 16:36:43 +0000</pubDate>
		<dc:creator>Multicore TechChannel</dc:creator>
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			<content:encoded><![CDATA[Insight from NEI on transitioning to Sandy Bridge. <a href="http://www.linkedin.com/news?viewArticle&amp;articleID=5576371474383507476&amp;gid=1854274&amp;type=member&amp;item=95804487&amp;articleURL=http%3A%2F%2Fblog.nei.com%2F2012%2F02%2F17%2Ftransitioning-to-sandy-bridge-intels-new-microarchitecture%2F&amp;urlhash=mo3h&amp;goback=.gde_1854274_member_95804487"  rel="nofollow nofollow" onmousedown="UntrustedLink.bootstrap($(this), &quot;mAQHaBOLG&quot;, event, bagof(&#123;&#125;));">http://www.linkedin.com/news?viewArticle&amp;articleID=5576371474383507476&amp;gid=1854274&amp;type=member&amp;item=95804487&amp;articleURL=http%3A%2F%2Fblog.nei.com%2F2012%2F02%2F17%2Ftransitioning-to-sandy-bridge-intels-new-microarchitecture%2F&amp;urlhash=mo3h&amp;goback=.gde_1854274_member_95804487</a><br/><br/><br/><a href="http://www.linkedin.com/news?viewArticle&amp;articleID=5576371474383507476&amp;gid=1854274&amp;type=member&amp;item=95804487&amp;articleURL=http%3A%2F%2Fblog.nei.com%2F2012%2F02%2F17%2Ftransitioning-to-sandy-bridge-intels-new-microarchitecture%2F&amp;urlhash=mo3h&amp;goback=.gde_1854274_member_95804487" id=""  style="" onmousedown="UntrustedLink.bootstrap($(this), &quot;1AQE07mq2&quot;, event, bagof(&#123;&#125;));" rel="nofollow">CompactPCI, AdvancedTCA, MicroTCA Group News | LinkedIn</a><br/>www.linkedin.com]]></content:encoded>
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		<title>Real-time performance: Build or buy?</title>
		<link>http://embedded-computing.com/real-time-performance-build-buy</link>
		<comments>http://embedded-computing.com/real-time-performance-build-buy#comments</comments>
		<pubDate>Tue, 07 Feb 2012 15:00:00 +0000</pubDate>
		<dc:creator>Warren Webb, Editorial Director</dc:creator>
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		<guid isPermaLink="false">http://tech.opensystemsmedia.com/multicore/?guid=4eeea068122c248fac8f704316c81c09</guid>
		<description><![CDATA[Ever-growing demands and challenges could render in-house OS development a thing of the past.]]></description>
			<content:encoded><![CDATA[<div
class="story"><h3 class="abstract"><img
alt="3" class="figure_intro wide" src="http://i.opensystemsmedia.com/?zc=F&#038;f=png&#038;h=320&#038;w=600&#038;src=http%3A%2F%2Fattachments.opensystemsmedia.com%2FECD5527%2Ffigures%2F3" />As more and more embedded devices evolve from single-function controllers to complex platforms supporting high-speed graphics, user interfaces, and network communications in addition to the primary application, real-time responsiveness is becoming a critical performance requirement. Although developing in-house software offers some advantages, the benefits of reduced complexity and shorter development schedules often justify the purchase of a commercial Real-Time Operating System.</h3><p><span
id="more-468015"></span><span
class='body'><p
class="body-text">The average person interacts with hundreds of embedded processors every day in phones, automobiles, home appliances, toys, cash registers, entertainment electronics, <a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#security%20systems">security systems</a>, environmental controls, and personal electronics. The common link among all of these products is their ability to react in <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#real%20time">real time</a> to the user, external events, and the communications channel.</p><p
class="body-text">The software for these embedded devices can be divided into application software and <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#operating%20system">Operating System</a> (OS) software. Application software makes the product unique and contains the data collection, <a
rel="tag" href="http://channels.opensystemsmedia.com/Radar">signal processing</a>, and hardware control routines required to make the product perform to its specification. The OS allows the programmer to break up large application programs into smaller, individually developed processes or tasks.</p><p
class="body-text">At the heart of an OS is the kernel, which schedules programs for execution and manages shared resources. A Real-Time OS (<a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#rtos">RTOS</a>) processes hardware requests or interrupts from timers or external events within a guaranteed maximum time. Programmers interact with the OS&nbsp;through an API and set up the priorities and data dependencies. During execution, the RTOS manages the application software with a flurry of external real-time activity.</p><p
class="heading-1">In-house code</p><p
class="body-text">Even with the advantages of an RTOS, homegrown OSs still occupy a non-trivial percentage of embedded real-time products. Developers have multiple incentives for bypassing a commercial RTOS entirely and writing their own real-time routines. The biggest reason developers cite for not choosing a commercial OS is lack of need. With only one task running, designers think they can easily keep track of the required hardware interaction.</p><p
class="body-text">Special situations sometimes justify in-house software. For example, the design objectives of a portable <a
rel="tag" href="http://channels.opensystemsmedia.com/health%20care">health care</a> device can include low cost, low power, and a one-year battery standby life without extra memory and processing power to support a commercial RTOS. Furthermore, if a new project is an upgrade of a previous project, developers likely will want to use as much legacy code as possible.</p><p
class="body-text">Components that aren&#8217;t invented at the same company might also be one reason why many developers write their own OSs. Installing software from a third party into their showpiece product is like admitting they are somehow not up to the task. In addition, developers might think they&#8217;ll lose the ability to make software adjustments to compensate for hardware changes or to correct bugs. The designer can easily adjust the order of execution or drop to assembly language to solve critical timing problems with in-house developed software. However, with a commercial RTOS, the scheduler handles many of the timing issues, so developers lose the perception of being in total control. And finally, programmers list sticker shock as another reason to write their own operating software. The initial license for a full commercial RTOS and associated tools can be in the $15,000 to $20,000&nbsp;range for a single development seat, plus recurring royalties for every unit shipped.</p><p
class="heading-1">Software shortcuts</p><p
class="body-text">As <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20systems">embedded systems</a> grow in complexity and project schedules shrink, software has displaced hardware as the highest-priced item in most embedded development projects. If design teams can buy an RTOS and eliminate the coding, <a
rel="tag" href="http://channels.opensystemsmedia.com/Diagnostics">debug</a>, and documentation of the most complicated portion of the software structure, then the purchase decision should receive careful consideration. Although a commercial RTOS can be expensive, a smaller development team and shorter project time frame might create more than enough savings to justify the purchase.</p><p
class="body-text">An RTOS allows programmers to write independent, reusable modules to reduce software complexity and shorten the development schedule. Programmers can write each software routine independently without getting bogged down with intertask timing problems. Most RTOS vendors provide a full interactive development environment including a source code editor, code manager, linker, downloader, runtime tools, and one or more debuggers. Software vendors also supply software performance analysis tools to help profile and visualize real-time activity in application routines. Programmers can monitor which tasks are running, observe the stream of data flow, and detect when and how often a task is interrupted by a higher-priority item. RTOS vendors agree that high-quality development tools can dramatically shorten debug time.</p><p
class="body-text">Along with the cost savings, RTOS vendors cite multiple technical reasons to justify their products. For example, if an application involves heavy data processing, many RTOSs can be scaled easily to spread tasks across several processors for a significant performance boost. The RTOS provides communication and <a
rel="tag" href="http://channels.opensystemsmedia.com/10%20Gigabit%20Ethernet">synchronization</a> services to make multiprocessing <a
rel="tag" href="http://tech.opensystemsmedia.com/cloud/#transparent">transparent</a>. In addition, an off-the-shelf RTOS working alongside <a
rel="tag" href="http://tech.opensystemsmedia.com/multicore/">multicore</a><span
class="social" style="margin:0 0 0 3px">[<a
href="http://opsy.st/multicore-facebook"><img
style="margin:0 2px -2px 2px;vertical-align:baseline" src="http://i.opensystemsmedia.com/i/a-facebook-12x12.gif" /></a>]</span> processors simplifies legacy code integration within new designs or products updates.</p><p
class="body-text">A commercial RTOS is modular, so users can select only those portions or features of the OS that they need. Specifying a subset of the full-blown commercial RTOS can reduce acquisition costs and the required memory footprint. With the current connectivity trend, even the simplest embedded products might need to connect to and send data over the Internet. A graphical user interface could also become standard in small embedded systems, even if just for maintenance. These features are included or optionally available in most commercial RTOSs, but can be very expensive or impossible to&nbsp;add to a proprietary OS. Vendors also promote product on-demand technical support as a major benefit of a commercial RTOS.</p><p
class="heading-1">Off-the-shelf platforms</p><p
class="body-text">Commercial RTOSs are constantly upgraded to add new features and keep up with changing technology. For example, the popular <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#vxworks%20os">VxWorks OS</a> from Wind River was recently revised to deliver 64-bit computing support along with improved multicore features. <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#vxworks">VxWorks</a> includes a shell, <a
rel="tag" href="http://channels.opensystemsmedia.com/Diagnostics">debugging</a> functions, memory management, performance monitoring, and support for multiprocessing. Real-time features include a kernel for preemptive <a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/#multitasking">multitasking</a>, interrupt response, interprocess communication, and a file system (see block diagram in Figure 1). Software development is enabled by the Wind&nbsp;River Workbench development tools suite and Intel Integrated Performance Primitives for VxWorks.</p><p
class="figures"> <figure></p><table
width="480" border="0" align="center" cellpadding="2" cellspacing="0"><tr><td
align="center" ><p> <a
onclick="popup=window.open(this.href, 'Figure1', 'width=875,height=977,scrollbars=no,resizable=yes'); popup.focus(); return false;" id="Figure1" href="http://i.opensystemsmedia.com/?bg=ffffff&#038;q=90&#038;w=871&#038;f=jpg&#038;src=http%3A%2F%2Fattachments.opensystemsmedia.com%2FECD5527%2Ffigures%2F1" title="The VxWorks RTOS from Wind River fits many embedded applications and features 32-bit or 64-bit processing, multicore support, and numerous connectivity options."><br
/> <img
width="470" border="0" alt="Figure1" src="http://i.opensystemsmedia.com/?q=94&#038;bg=ffffff&#038;w=470&#038;f=jpg&#038;src=http%3A%2F%2Fattachments.opensystemsmedia.com%2FECD5527%2Ffigures%2F1" /><br
/> </a></td></tr><tr><td
class="caption" align="center" style="padding-top: 11px; line-height: 1em;"> <figcaption><b>Figure 1:</b> The VxWorks RTOS from Wind River fits many embedded applications and features 32-bit or 64-bit processing, multicore support, and numerous connectivity options.</figcaption><div
style="color: #336600; padding-top: 4px; font-size: 9px;"><b>(click graphic to zoom)</b></div></td></tr></table><p> </figure></p><p
class="body-text">The RTOS supports various multicore configurations in Symmetrical Multi-Processing (SMP) and Asymmetrical Multi-Processing (AMP) modes or as a guest OS on top of Wind River <a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/#hypervisor">Hypervisor</a>. VxWorks also has a configurable and tunable small memory footprint, allowing the user to control how much of the OS to employ for each project.</p><p
class="body-text">In addition to offering a multitude of commercial RTOS products, the embedded systems community maintains an open-source OS based on a real-time kernel that is free for use in commercial applications. The FreeRTOS&nbsp;Project is under continuous active development and is distributed under the GNU General Public License with an optional exception that allows users to keep their proprietary software confidential. Free source code and the lack of recurring royalties are popular features for small, low-budget embedded projects. FreeRTOS has been ported to multiple <a
rel="tag" href="http://channels.opensystemsmedia.com/microcontroller">microcontroller</a> platforms and has minimal ROM, RAM, and processing overhead, resulting in a typical kernel binary image in the 4 KB to 9 KB range. Although FreeRTOS source code for the kernel is contained in only three C&nbsp;code files, the zip file download includes numerous demonstration applications to help new users get started.</p><p
class="body-text">The biggest complaint among potential <a
rel="tag" href="http://tech.opensystemsmedia.com/cloud/#open-source%20software">open-source software</a> users is the lack of a central resource to provide support similar to that offered by a commercial software vendor; however, the FreeRTOS website has an active free support forum where developers can find answers to their technical questions. In support of the open-source platform, Microchip Technology offers the FreeRTOS Microchip PIC32 Education Kit (see Figure 2). This $95 kit includes a development board that enables users to develop USB embedded host, device, and On-The-Go applications on the PIC32 microcontroller family.</p><p
class="figures"> <figure></p><table
width="480" border="0" align="center" cellpadding="2" cellspacing="0"><tr><td
align="center" ><p> <a
onclick="popup=window.open(this.href, 'Figure2', 'width=875,height=738,scrollbars=no,resizable=yes'); popup.focus(); return false;" id="Figure2" href="http://i.opensystemsmedia.com/?bg=ffffff&#038;q=90&#038;w=871&#038;f=jpg&#038;src=http%3A%2F%2Fattachments.opensystemsmedia.com%2FECD5527%2Ffigures%2F2" title="The Microchip PIC32 Education Kit includes the hardware, software, and tutorials needed to get started using the open-source FreeRTOS platform."><br
/> <img
width="470" border="0" alt="Figure2" src="http://i.opensystemsmedia.com/?q=94&#038;bg=ffffff&#038;w=470&#038;f=jpg&#038;src=http%3A%2F%2Fattachments.opensystemsmedia.com%2FECD5527%2Ffigures%2F2" /><br
/> </a></td></tr><tr><td
class="caption" align="center" style="padding-top: 11px; line-height: 1em;"> <figcaption><b>Figure 2:</b> The Microchip PIC32 Education Kit includes the hardware, software, and tutorials needed to get started using the open-source FreeRTOS platform.</figcaption><div
style="color: #336600; padding-top: 4px; font-size: 9px;"><b>(click graphic to zoom by 1.9x)</b></div></td></tr></table><p> </figure></p><p
class="heading-1">Real-time future</p><p
class="body-text">Although programmers might get excited when considering the challenge of developing an in-house OS, the &#8220;roll&nbsp;your own&#8221; days might be fading away. Designers can look forward to real-time software as the norm in future embedded products.</p><p
class="body-text">Customer demand for faster response times, complex functionality, and instant data access continues to increase the challenge of <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20design">embedded design</a>. Advancing technology also dictates that embedded products be capable of periodic software updates as requirements change, along with the possible transfer to the next-generation hardware platform.</p><p
class="body-text">Developers should take the time to analyze their system requirements, development schedule, software support, expandability, communications, scalability, and future growth before embarking on an in-house software development project. An off-the-shelf commercial RTOS or even an open-source operating system could be in your future.</p></p></div><p></span></div></p><div
class="keywords"><h2>Topics covered in this article</h2><ul><li><a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#security%20systems">security systems</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#real%20time">real time</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Radar">signal processing</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#operating%20system">operating system</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#rtos">rtos</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/health%20care">health care</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20systems">embedded systems</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Diagnostics">debug</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/10%20Gigabit%20Ethernet">synchronization</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/cloud/#transparent">transparent</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/multicore/">multicore</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/#multitasking">multitasking</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#vxworks%20os">vxworks os</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Diagnostics">debugging</a></li><li><a
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rel="tag" href="http://tech.opensystemsmedia.com/virtualization/#hypervisor">hypervisor</a></li><li><a
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rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20design">embedded design</a></li></ul></div>]]></content:encoded>
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		<title>Roving Reporter: Verifying code performance on multicore devices</title>
		<link>http://embedded-computing.com/roving-code-performance-multicore-devices</link>
		<comments>http://embedded-computing.com/roving-code-performance-multicore-devices#comments</comments>
		<pubDate>Fri, 13 Jan 2012 23:13:33 +0000</pubDate>
		<dc:creator>Warren Webb, Editorial Director</dc:creator>
				<category><![CDATA[Blog]]></category>
		<category><![CDATA[Columns]]></category>

		<guid isPermaLink="false">http://embedded.communities.intel.com/community/en/software/blog/2012/01/13/roving-reporter-verifying-code-performance-on-multicore-devices</guid>
		<description><![CDATA[<div><p>As designers transition to the latest generation multicore processors, software must be divided into separate partitions to gain the performance benefits of parallel execution.&#160; With Intel&#174; Core&#8482; processors, developers have access to multiple techniques to enable this performance gain including symmetric or asymmetric multiprocessing and virtualization. In the symmetric multiprocessing (SMP) configuration, a single operating system allocates threads or tasks across the available cores while managing common memory and hardware resources. Asymmetric multiprocessing (AMP) allows each core to run independent software so that a single system can easily combine real-time, deterministic tasks with a graphical user interface. With virtualization, a hypervisor isolates and allocates system resources between the operating environments so that real-time, general-purpose, and legacy software can be readily integrated in a multicore system.</p><p>&#160;</p><p>Each of these performance improvement techniques has some risks especially for safety-critical applications. For example, when parallel, multithreaded applications become part of the software structure they are vulnerable to &#8220;race conditions&#8221; which occur when concurrent routines have access to, and one of them modifies, a shared memory location. Software failures and bugs caused by these race conditions are not deterministic and may be extremely difficult to locate with normal testing procedures. When developing parallel software, programmers must anticipate these simultaneous activities and once a routine begins to access memory, it must lock out other activities until the transaction is completed.&#160; Although this approach sounds feasible, in practice it may run into problems if two routines are trying to &#8220;lock out&#8221; other activities simultaneously. To tackle these somewhat subtle coding problems, a number of software vendors have integrated analysis tools into their development packages to optimize the transition from serial applications to parallelism.</p><p>&#160;</p><p>For C, C++, Java, and C# software development projects, <a rel="nofollow" target="_blank" href="http://www.klocwork.com/">Klocwork</a> offers the <a rel="nofollow" target="_blank" href="http://www.klocwork.com/products/insight/index.php">Insight</a> static code analysis tools to automatically locate critical programming bugs and security vulnerabilities in source code (See figure 1).&#160; Klocwork has developed several approaches to locate and eliminate coding problems associated with multicore architectures. In a whitepaper entitled &#8220;<a rel="nofollow" target="_blank" href="http://www.klocwork.com/resources/white-paper/endian-concurrency-analysis">Developing Software in a Multicore &#038; Multiprocessor World</a>&#8221;, Klocwork CTO Gwyn Fisher discusses techniques to identify unique software problems - specifically concurrency errors and endian incompatibilities. The paper also cites a <a rel="nofollow" target="_blank" href="http://www.vdcresearch.com/market_research/embedded_software/research_reports.aspx">VDC Research report</a> that multicore and multiprocessor software projects are 4.5 times more expensive and have 25% longer schedules than the single core equivalents. In addition, Klocwork offers an <a rel="nofollow" target="_blank" href="http://www.klocwork.com/resources/on-demand-webinar/tag/multicore/multiprocessor-architectures">on-demand webinar</a> outlining the complexity of porting software to multiprocessor architectures and demonstrating the use of their <a rel="nofollow" target="_blank" href="http://www.klocwork.com/products/insight/klocwork-truepath/index.php">Truepath</a> automated, whole-program analysis engine.</p><p>&#160;</p><p><a rel="nofollow" target="_blank" href="http://embedded.communities.intel.com/servlet/JiveServlet/showImage/38-5316-3182/Klocwork-insight-config.png"><img alt="Klocwork-insight-config.png" class="jive-image-thumbnail jive-image" height="204" src="http://embedded.communities.intel.com/servlet/JiveServlet/downloadImage/38-5316-3182/450-204/Klocwork-insight-config.png" width="450" /></a></p><p>&#160;</p><p>Unlike other source code analyzers that run as separate tools, <a rel="nofollow" target="_blank" href="http://www.ghs.com/products/doublecheck.html">DoubleCheck</a> from Green Hills Software is an integrated static analyzer built directly into the <a rel="nofollow" target="_blank" href="http://www.ghs.com/products/MULTI_IDE.html">MULTI Integrated Development Environment</a> allowing compilation and defect analysis in the same pass. DoubleCheck evaluates potential execution paths through the code to determine how the values of program variables could change across these paths. To simplify the debugging of complex projects with multiple threads of execution, multiple cores, or multiple boards, the Green Hills <a rel="nofollow" target="_blank" href="http://www.ghs.com/products/MULTI_IDE.html">Integrated Target List</a> displays all system components hierarchically, making it easier to see relationships among applications, address spaces, tasks, and threads (See figure 2). Status information is displayed for all components, so you can quickly check the system state. The target list in the debugger allows you to follow application execution from one context to another with a single click. You can watch as different threads interact and sort out complex interdependencies easily.</p><p>&#160;</p><p><a rel="nofollow" target="_blank" href="http://embedded.communities.intel.com/servlet/JiveServlet/showImage/38-5316-3183/target_list.jpg"><img alt="target_list.jpg" class="jive-image" height="504" src="http://embedded.communities.intel.com/servlet/JiveServlet/downloadImage/38-5316-3183/450-504/target_list.jpg" width="450" /></a></p><p>&#160;</p><p>After software has been successfully divided into secure code segments using static analysis tools, the 2nd generation Intel&#174; Core&#8482; architecture provides multiple features that augment the performance benefits of parallel execution.&#160; For example, specialized Intel&#174; functions such as Extended Page Tables (EPT) and Page Attribute Table (PAT) provide a hardware assist to the partitioning and allocation of physical memory among multiple cores. The processors also feature <a rel="nofollow" target="_blank" href="http://www.intel.com/technology/virtualization/technology.htm?iid=tech_vt+tech">Intel&#174; Virtualization Technology</a> for flexible virtualization and <a rel="nofollow" target="_blank" href="http://www.intel.com/content/www/us/en/io/quickpath-technology/quickpath-technology-general.html">Intel&#174; QuickPath Technology</a> to maximize multi-core performance.&#160; If you are starting a new multicore project with and you have questions about static analysis tools, please share your concerns with fellow followers of the <a rel="nofollow" target="_blank" href="http://community.edc.intel.com/">Intel&#174; Embedded Community</a>. You can also keep up with the latest technical details and product announcements at the Embedded Computing Design archives on <a rel="nofollow" target="_blank" href="http://embedded-computing.com/?s=multi+core+static+code+analysis">Multicore static code analysis</a>.</p><p>&#160;</p><p>To view other community content on interoperability, see "<a rel="nofollow" target="_blank" href="http://embedded.communities.intel.com/docs/DOC-6850">Interoperability - Top Picks</a>&#8221;</p><p><a rel="nofollow" target="_blank" href="http://embedded.communities.intel.com/servlet/JiveServlet/showImage/38-5316-3184/interoperability.jpg"><img alt="interoperability.jpg" class="jive-image" height="35" src="http://embedded.communities.intel.com/servlet/JiveServlet/downloadImage/38-5316-3184/48-35/interoperability.jpg" width="48" /></a></p><p>Warren Webb<br />OpenSystems Media&#174;, by special arrangement with Intel&#174; Embedded Alliance</p><p>&#160;</p><p>Klocwork and Green Hills Software are<em> Affiliate members of the by Intel&#174; Embedded Alliance. </em></p></div>]]></description>
			<content:encoded><![CDATA[<div
class="jive-rendered-content"><p>As designers transition to the latest generation multicore processors, software must be divided into separate partitions to gain the performance benefits of parallel execution.&#160; With Intel&#174; Core&trade; processors, developers have access to multiple techniques to enable this performance gain including symmetric or <a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/#asymmetric%20multiprocessing">asymmetric multiprocessing</a> and virtualization. In the <a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/#symmetric%20multiprocessing">symmetric multiprocessing</a> (SMP) configuration, a single <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#operating%20system">operating system</a> allocates threads or tasks across the available cores while managing common memory and hardware resources. Asymmetric multiprocessing (AMP) allows each core to run independent software so that a single system can easily combine real-time, deterministic tasks with a graphical user interface. With virtualization, a <a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/#hypervisor">hypervisor</a> isolates and allocates system resources between the operating environments so that real-time, general-purpose, and legacy software can be readily integrated in a multicore system.</p><p
style="min-height:8pt;height:8pt;padding:0px;">&#160;</p><p>Each of these performance improvement techniques has some risks especially for <a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#safety-critical">safety-critical</a> applications. For example, when parallel, multithreaded applications become part of the software structure they are vulnerable to &ldquo;race conditions&#8221; which occur when concurrent routines have access to, and one of them modifies, a shared memory location. Software failures and bugs caused by these race conditions are not deterministic and may be extremely difficult to locate with normal testing procedures. When developing parallel software, programmers must anticipate these simultaneous activities and once a routine begins to access memory, it must lock out other activities until the transaction is completed.&#160; Although this approach sounds feasible, in practice it may run into problems if two routines are trying to &ldquo;lock out&#8221; other activities simultaneously. To tackle these somewhat subtle coding problems, a number of software vendors have integrated analysis tools into their development packages to optimize the transition from serial applications to parallelism.</p><p
style="min-height:8pt;height:8pt;padding:0px;">&#160;</p><p>For C, C++, <a
rel="tag" href="http://channels.opensystemsmedia.com/Java">Java</a>, and C# software development projects, <a
rel="nofollow" class="jive-link-external-small"  href="http://www.klocwork.com/">Klocwork</a> offers the <a
rel="nofollow" class="jive-link-external-small"  href="http://www.klocwork.com/products/insight/index.php">Insight</a> static code analysis tools to automatically locate critical programming bugs and <a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#security">security</a> vulnerabilities in source code (See figure 1).&#160; Klocwork has developed several approaches to locate and eliminate coding problems associated with multicore architectures. In a whitepaper entitled &ldquo;<a
rel="nofollow" class="jive-link-external-small"  href="http://www.klocwork.com/resources/white-paper/endian-concurrency-analysis">Developing Software in a Multicore &amp; Multiprocessor World</a>&#8221;, Klocwork CTO Gwyn Fisher discusses techniques to identify unique software problems &#8211; specifically concurrency errors and endian incompatibilities. The paper also cites a <a
rel="nofollow" class="jive-link-external-small"  href="http://www.vdcresearch.com/market_research/embedded_software/research_reports.aspx">VDC Research report</a> that multicore and multiprocessor software projects are 4.5 times more expensive and have 25% longer schedules than the single core equivalents. In addition, Klocwork offers an <a
rel="nofollow" class="jive-link-external-small"  href="http://www.klocwork.com/resources/on-demand-webinar/tag/multicore/multiprocessor-architectures">on-demand webinar</a> outlining the complexity of porting software to multiprocessor architectures and demonstrating the use of their <a
rel="nofollow" class="jive-link-external-small"  href="http://www.klocwork.com/products/insight/klocwork-truepath/index.php">Truepath</a> automated, whole-program analysis engine.</p><p
style="min-height:8pt;height:8pt;padding:0px;">&#160;</p><p><a
rel="nofollow"  href="http://embedded.communities.intel.com/servlet/JiveServlet/showImage/38-5316-3182/Klocwork-insight-config.png"><img
alt="Klocwork-insight-config.png" class="jive-image-thumbnail jive-image" height="204" src="http://embedded.communities.intel.com/servlet/JiveServlet/downloadImage/38-5316-3182/450-204/Klocwork-insight-config.png" width="450"/></a></p><p
style="min-height:8pt;height:8pt;padding:0px;">&#160;</p><p>Unlike other source code analyzers that run as separate tools, <a
rel="nofollow" class="jive-link-external-small"  href="http://www.ghs.com/products/doublecheck.html">DoubleCheck</a> from Green Hills Software is an integrated static analyzer built directly into the <a
rel="nofollow" class="jive-link-external-small"  href="http://www.ghs.com/products/MULTI_IDE.html">MULTI Integrated Development Environment</a> allowing compilation and defect analysis in the same pass. DoubleCheck evaluates potential execution paths through the code to determine how the values of program variables could change across these paths. To simplify the <a
rel="tag" href="http://channels.opensystemsmedia.com/Diagnostics">debugging</a> of complex projects with multiple threads of execution, multiple cores, or multiple boards, the Green Hills <a
rel="nofollow" class="jive-link-external-small"  href="http://www.ghs.com/products/MULTI_IDE.html">Integrated Target List</a> displays all system components hierarchically, making it easier to see relationships among applications, address spaces, tasks, and threads (See figure 2). Status information is displayed for all components, so you can quickly check the system state. The target list in the debugger allows you to follow application execution from one context to another with a single click. You can watch as different threads interact and sort out complex interdependencies easily.</p><p
style="min-height:8pt;height:8pt;padding:0px;">&#160;</p><p><a
rel="nofollow"  href="http://embedded.communities.intel.com/servlet/JiveServlet/showImage/38-5316-3183/target_list.jpg"><img
alt="target_list.jpg" class="jive-image" height="504" src="http://embedded.communities.intel.com/servlet/JiveServlet/downloadImage/38-5316-3183/450-504/target_list.jpg" width="450"/></a></p><p
style="min-height:8pt;height:8pt;padding:0px;">&#160;</p><p>After software has been successfully divided into <a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#secure">secure</a> code segments using <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#static%20analysis">static analysis</a> tools, the 2nd generation Intel&#174; Core&trade; architecture provides multiple features that augment the performance benefits of parallel execution.&#160; For example, specialized Intel&#174; functions such as Extended Page Tables (EPT) and Page Attribute Table (PAT) provide a hardware assist to the partitioning and allocation of physical memory among multiple cores. The processors also feature <a
rel="nofollow" class="jive-link-external-small"  href="http://www.intel.com/technology/virtualization/technology.htm?iid=tech_vt+tech">Intel&#174; Virtualization Technology</a> for flexible virtualization and <a
rel="nofollow" class="jive-link-external-small"  href="http://www.intel.com/content/www/us/en/io/quickpath-technology/quickpath-technology-general.html">Intel&#174; QuickPath Technology</a> to maximize multi-core performance.&#160; If you are starting a new multicore project with and you have questions about static analysis tools, please share your concerns with fellow followers of the <a
rel="nofollow" class="jive-link-external-small"  href="http://community.edc.intel.com/">Intel&#174; Embedded Community</a>. You can also keep up with the latest technical details and product announcements at the Embedded Computing Design archives on <a
rel="nofollow" class="jive-link-external-small"  href="http://embedded-computing.com/?s=multi+core+static+code+analysis">Multicore static code analysis</a>.</p><p
style="min-height:8pt;height:8pt;padding:0px;">&#160;</p><p>To view other community content on interoperability, see &#8220;<a
rel="nofollow" class=""  href="http://embedded.communities.intel.com/docs/DOC-6850">Interoperability &#8211; Top Picks</a>&#8221;</p><p><a
rel="nofollow"  href="http://embedded.communities.intel.com/servlet/JiveServlet/showImage/38-5316-3184/interoperability.jpg"><img
alt="interoperability.jpg" class="jive-image" height="35" src="http://embedded.communities.intel.com/servlet/JiveServlet/downloadImage/38-5316-3184/48-35/interoperability.jpg" width="48"/></a></p><p>Warren Webb<br/>OpenSystems Media&#174;, by special arrangement with Intel&#174; Embedded Alliance</p><p
style="min-height:8pt;height:8pt;padding:0px;">&#160;</p><p>Klocwork and Green Hills Software are<em> Affiliate members of the by Intel&#174; Embedded Alliance. </em></p></div></p><div
class="keywords"><h2>Topics covered in this article</h2><ul><li><a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/#asymmetric%20multiprocessing">asymmetric multiprocessing</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/#symmetric%20multiprocessing">symmetric multiprocessing</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#operating%20system">operating system</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#safety-critical">safety-critical</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#static%20analysis">static analysis</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/#hypervisor">hypervisor</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Diagnostics">debugging</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#security">security</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#secure">secure</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Java">Java</a></li></ul></div> <script type="text/javascript">var found_terms = new Array("asymmetric multiprocessing","symmetric multiprocessing","operating system","safety-critical","static analysis","hypervisor","debugging","security","secure","Java");</script> ]]></content:encoded>
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		<title>Embedded goes virtual</title>
		<link>http://embedded-computing.com/embedded-goes-virtual</link>
		<comments>http://embedded-computing.com/embedded-goes-virtual#comments</comments>
		<pubDate>Fri, 09 Dec 2011 15:00:00 +0000</pubDate>
		<dc:creator>Warren Webb, Editorial Director</dc:creator>
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		<guid isPermaLink="false">http://tech.opensystemsmedia.com/multicore/?guid=629d61b896e902b60fb5fa8be2604cdd</guid>
		<description><![CDATA[Virtualization software facilitates the simplified design, easy upgradability, and increased optimization of embedded systems.]]></description>
			<content:encoded><![CDATA[<div
class="story"><h3 class="abstract"><img
alt="4" class="figure_intro wide" src="http://i.opensystemsmedia.com/?zc=F&#038;f=png&#038;h=320&#038;w=600&#038;src=http%3A%2F%2Fattachments.opensystemsmedia.com%2FECD5457%2Ffigures%2F4" />In embedded applications, virtualization software can be used to combine a real-time deterministic operating system with a high-level interactive operating system like Windows or Linux. Using virtualization platforms and tools such as those mentioned in the following discussion simplifies system upgrades and optimizes performance by independently allocating system resources to each operating environment.</h3><p><span
id="more-467287"></span><span
class='body'><p
class="body-text">As embedded technology and market expectations evolve, design engineers are constantly pressured to pack expanded functionality into smaller, reduced-power devices. In addition to the added complexity of the application software for these new projects, customers demand an interactive interface, ubiquitous connectivity, absolute <a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#security">security</a>, and extreme reliability.</p><p
class="body-text">Embedded designers also face the challenge of combining slower legacy interface circuitry with the latest high-speed control devices and multiple displays. The resulting system often includes the original hardware with its <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#operating%20system">Operating System</a> (OS) and application software, plus a completely separate controller with software to handle the newer requirements. This approach increases component count and power requirements and does nothing to increase legacy application performance.</p><p
class="body-text">To deal with this increased complexity, designers are utilizing <a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/#virtual">virtual</a> processors hosting multiple OSs to ensure unimpeded, deterministic response to real-time events while simultaneously providing users and operators with a high-level, <a
rel="tag" href="http://channels.opensystemsmedia.com/Gfx_Video">graphics</a>-based interface. <a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/">Virtualization</a><span
class="social" style="margin:0 0 0 3px">[<a
href="http://opsy.st/virtualization-facebook"><img
style="margin:0 2px -2px 2px;vertical-align:baseline" src="http://i.opensystemsmedia.com/i/a-facebook-12x12.gif" /></a>]</span> is achieved by adding a <a
rel="tag" href="http://channels.opensystemsmedia.com/Manycore">Virtual Machine Monitor</a> (<a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/#vmm">VMM</a>) software layer or <a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/#hypervisor">hypervisor</a> that isolates individual partitions and executes guest operating software. The hypervisor creates one or more simulated computer environments or virtual machines that can simultaneously host independent OSs and applications on a single processor.</p><p
class="body-text">To speed up virtual component interaction, silicon manufacturers are incorporating hardware-assisted virtualization in processor architectures tailored for extended <a
rel="tag" href="http://channels.opensystemsmedia.com/Obsolescence">life-cycle</a> embedded applications. For example, the second-generation Intel Core and Intel Atom E6xx processors support Intel Virtualization Technology (Intel VT). This technology improves software-based virtualization performance and security by using hardware assist to trap and execute certain VMM instructions. Intel VT allows the VMM to allocate&nbsp;memory and I/O devices to specific partitions, thus decreasing the processor load and reducing virtual machine switching times.</p><p
class="heading-1">Virtual isolation</p><p
class="body-text">Virtual platforms that combine real-time or <a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#safety-critical">safety-critical</a> embedded functions with a large graphics-based OS must contain security provisions that allow unaffected partitions to continue operation in the event of a software failure or <a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#cyber%20attack">cyber attack</a>. For example, <a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#lynuxworks">LynuxWorks</a> updated the LynxSecure <a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/#separation%20kernel">separation kernel</a> and hypervisor for various virtual machine configurations, as shown in Figure 1. This virtualization software is designed to operate in <a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#secure">secure</a> <a
rel="tag" href="http://channels.opensystemsmedia.com/Military">defense</a> environments where data and applications with different security levels must co-reside on a single device without corruption. LynxSecure uses a hypervisor to create a virtualization layer that maps physical system resources to each guest OS, which is assigned dedicated resources such as memory, CPU time, and I/O peripherals. Another key feature is the ability to run fully virtualized 64-bit guest OSs such as Windows 7, <a
rel="tag" href="http://tech.opensystemsmedia.com/linux/">Linux</a><span
class="social" style="margin:0 0 0 3px">[<a
href="http://opsy.st/linux-facebook"><img
style="margin:0 2px -2px 2px;vertical-align:baseline" src="http://i.opensystemsmedia.com/i/a-facebook-12x12.gif" /></a>]</span>, and Solaris <a
rel="tag" href="http://tech.opensystemsmedia.com/multicore/#across%20multiple%20cores">across multiple cores</a>.</p><p
class="figures"> <figure></p><table
width="480" border="0" align="center" cellpadding="2" cellspacing="0"><tr><td
align="center" ><p> <a
onclick="popup=window.open(this.href, 'Figure1', 'width=875,height=580,scrollbars=no,resizable=yes'); popup.focus(); return false;" id="Figure1" href="http://i.opensystemsmedia.com/?bg=ffffff&#038;q=90&#038;w=871&#038;f=jpg&#038;src=http%3A%2F%2Fattachments.opensystemsmedia.com%2FECD5457%2Ffigures%2F1" title="The LynxSecure embedded hypervisor allows multiple dissimilar OSs to share a single physical hardware platform."><br
/> <img
width="470" border="0" alt="Figure1" src="http://i.opensystemsmedia.com/?q=94&#038;bg=ffffff&#038;w=470&#038;f=jpg&#038;src=http%3A%2F%2Fattachments.opensystemsmedia.com%2FECD5457%2Ffigures%2F1" /><br
/> </a></td></tr><tr><td
class="caption" align="center" style="padding-top: 11px; line-height: 1em;"> <figcaption><b>Figure 1:</b> The LynxSecure embedded hypervisor allows multiple dissimilar OSs to share a single physical hardware platform.</figcaption><div
style="color: #336600; padding-top: 4px; font-size: 9px;"><b>(click graphic to zoom by 1.9x)</b></div></td></tr></table><p> </figure></p><p
class="body-text">TenAsys Corporation offers eVM for Windows, another embedded virtualization platform that hosts an <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20os">embedded OS</a> or Real-Time OS (<a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#rtos">RTOS</a>) alongside Windows on the same processor platform. To ensure that critical hardware interfaces are not virtualized, eVM partitions the platform, thus guaranteeing maximum performance and deterministic response to real-time events. Installed as a standard Windows application, eVM includes all of the integration tools needed to set up, start, and stop multiple RTOS guest configurations. The Windows-based control panel also allows users to assign interrupts, allocate I/O devices, and set up disk boot images. After the system is set up, eVM provides the guest RTOS with the lowest possible interrupt latency, direct access to I/O, and non-paged RAM.</p><p
class="heading-1"><a
rel="tag" href="http://tech.opensystemsmedia.com/multicore/">Multicore</a><span
class="social" style="margin:0 0 0 3px">[<a
href="http://opsy.st/multicore-facebook"><img
style="margin:0 2px -2px 2px;vertical-align:baseline" src="http://i.opensystemsmedia.com/i/a-facebook-12x12.gif" /></a>]</span> virtualization</p><p
class="body-text">Although virtualization allows designers to combine OSs and applications to reduce system power requirements and form factors, it does little to increase the performance of individual software components. One of the latest trends among designers is to incorporate multicore processors along with virtualization to boost performance through parallel processing.</p><p
class="body-text">With virtualization, the hypervisor isolates and allocates system resources between operating environments so that real-time, general-purpose, and legacy software can be readily integrated in a multicore system. In addition to memory and hardware device allocation, virtualization allows developers to assign multiple cores to compute-intensive applications as needed to maximize overall system performance.</p><p
class="body-text">Extending virtualization to multicore applications, the Wind River Hypervisor allows designers to configure and <a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#partition">partition</a> hardware devices, memory, and cores into virtual boards, each with its own OS, while maintaining the necessary separation (see Figure 2). These virtual boards can be run on a single processor core or distributed across multiple cores based on system needs. The Wind River Hypervisor has been applied in safety-critical applications where the system&#8217;s safety-certified and noncertified components traditionally had to be physically separated. However, embedded virtualization allows system designers to isolate the safety-certified components while still operating on a single hardware platform utilizing a certified hypervisor. Virtualization also improves the potential uptime of embedded applications by enabling individual partitions to be rebooted or even reprogrammed while other services on the same device are not affected.</p><p
class="figures"> <figure></p><table
width="480" border="0" align="center" cellpadding="2" cellspacing="0"><tr><td
align="center" ><p> <a
onclick="popup=window.open(this.href, 'Figure2', 'width=875,height=580,scrollbars=no,resizable=yes'); popup.focus(); return false;" id="Figure2" href="http://i.opensystemsmedia.com/?bg=ffffff&#038;q=90&#038;w=871&#038;f=jpg&#038;src=http%3A%2F%2Fattachments.opensystemsmedia.com%2FECD5457%2Ffigures%2F2" title="The Wind River Hypervisor provides a virtualization layer that partitions a single or multicore chip into multiple partitions with varying levels of protection and capabilities."><br
/> <img
width="470" border="0" alt="Figure2" src="http://i.opensystemsmedia.com/?q=94&#038;bg=ffffff&#038;w=470&#038;f=jpg&#038;src=http%3A%2F%2Fattachments.opensystemsmedia.com%2FECD5457%2Ffigures%2F2" /><br
/> </a></td></tr><tr><td
class="caption" align="center" style="padding-top: 11px; line-height: 1em;"> <figcaption><b>Figure 2:</b> The Wind River Hypervisor provides a virtualization layer that partitions a single or multicore chip into multiple partitions with varying levels of protection and capabilities.</figcaption><div
style="color: #336600; padding-top: 4px; font-size: 9px;"><b>(click graphic to zoom by 1.9x)</b></div></td></tr></table><p> </figure></p><p
class="body-text">Real-Time Systems also provides virtualization support for multicore processors. Leveraging Intel VT for security, the RTS Real-Time Hypervisor allows completely independent execution of more than one OS on a single <a
rel="tag" href="http://tech.opensystemsmedia.com/multicore/#multicore%20platform">multicore platform</a>. Designers can assign individual processor cores, memory, and devices to each OS. Through a configuration file, the boot sequence can be specified, and when desired, an operating system can be rebooted independently of the others. To facilitate communication between OSs, the hypervisor also provides configurable user-shared memory, as well as a <a
rel="tag" href="http://channels.opensystemsmedia.com/Network%20testing">TCP</a>/IP-based virtual network driver. The system can run multiple instances of RTOSs mixed with high-level operating software such as Windows XP/<a
rel="tag" href="http://channels.opensystemsmedia.com/Windows%20CE">CE</a>/7/Embedded, QNX, Linux, On Time RTOS-32, <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#vxworks">VxWorks</a>, Microware OS-9, and <a
rel="tag" href="http://tech.opensystemsmedia.com/android/">Android</a><span
class="social" style="margin:0 0 0 3px">[<a
href="http://opsy.st/android-facebook"><img
style="margin:0 2px -2px 2px;vertical-align:baseline" src="http://i.opensystemsmedia.com/i/a-facebook-12x12.gif" /></a>]</span>.</p><p
class="heading-1">Development and <a
rel="tag" href="http://channels.opensystemsmedia.com/Diagnostics">debug</a></p><p
class="body-text">No matter if virtual applications run on a single processor or across multiple cores, software development and <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#debug%20tools">debug tools</a> must be configured to support more than one OS and memory partition. For example, Green Hills Software updated its INTEGRITY RTOS and MULTI Integrated Development Environment (IDE) to support the latest virtualization microarchitecture. INTEGRITY RTOS is built around a partitioning architecture to provide <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20systems">embedded systems</a> with enhanced reliability, security, and real-time performance. Secure partitions guarantee each task the resources it needs to protect the OS and user tasks from errant and <a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#malicious%20code">malicious code</a>. INTEGRITY architecture provides Asymmetrical Multi-Processing (AMP) and Symmetrical Multi-Processing (SMP) support optimized for embedded and real-time multicore processors.</p><p
class="body-text">MULTI IDE software tools include several C compiler options, a debugger, editor, configuration manager, code browser, and debugger in a single package. MULTI also features DoubleCheck, an integrated static analyzer that isolates bugs caused by complex interactions between code segments that might not be in the same source file. In addition, Green Hills Probe provides a multicore debug control for board bring-up, device driver development, and system-level <a
rel="tag" href="http://channels.opensystemsmedia.com/Diagnostics">debugging</a>.</p><p
class="body-text">The next step is to incorporate multicore support by updating and streamlining the software development tool set while minimizing modifications to current code creation practices. Various software vendors provide advanced development tools and board support packages for products based on second-generation Intel Core devices. For example, the Prism <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#software%20analysis">software analysis</a> tool from CriticalBlue (Figure 3) allows developers to analyze existing software applications, evaluate benefits of the new architecture, and select the appropriate processor.</p><p
class="figures"> <figure></p><table
width="480" border="0" align="center" cellpadding="2" cellspacing="0"><tr><td
align="center" ><p> <a
onclick="popup=window.open(this.href, 'Figure3', 'width=875,height=762,scrollbars=no,resizable=yes'); popup.focus(); return false;" id="Figure3" href="http://i.opensystemsmedia.com/?bg=ffffff&#038;q=90&#038;w=871&#038;f=jpg&#038;src=http%3A%2F%2Fattachments.opensystemsmedia.com%2FECD5457%2Ffigures%2F3" title="The Prism analysis package allows developers to emulate the numbers of cores, threads, and dependencies in the system to streamline the transition from sequential to parallel programming."><br
/> <img
width="470" border="0" alt="Figure3" src="http://i.opensystemsmedia.com/?q=94&#038;bg=ffffff&#038;w=470&#038;f=jpg&#038;src=http%3A%2F%2Fattachments.opensystemsmedia.com%2FECD5457%2Ffigures%2F3" /><br
/> </a></td></tr><tr><td
class="caption" align="center" style="padding-top: 11px; line-height: 1em;"> <figcaption><b>Figure 3:</b> The Prism analysis package allows developers to emulate the numbers of cores, threads, and dependencies in the system to streamline the transition from sequential to parallel <a
rel="tag" href="http://channels.opensystemsmedia.com/MATLAB">programming</a>.</figcaption><div
style="color: #336600; padding-top: 4px; font-size: 9px;"><b>(click graphic to zoom)</b></div></td></tr></table><p> </figure></p><p
class="body-text">Prism analyzes the behavior of existing code running on simulators or hardware development boards to assess opportunities that introduce or add further parallel code structures. For example, developers can select the appropriate member of the second-generation Intel Core processor family and analyze the impact of Intel Hyper-Threading Technology, data cache misses, and instruction throughput. Prism gives developers an estimate of the performance gain achievable by partitioning the program into multiple threads.</p><p
class="heading-1">Design simplified, performance&nbsp;optimized</p><p
class="body-text">Virtualization is a proven way to simplify <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20designs">embedded designs</a> with fewer components while integrating the framework needed to easily combine disparate operating software or future updates. Virtualization also simplifies system upgrades by isolating the hardware and software layers so that designers can easily add or modify peripherals, memory, and cores without restructuring the software architecture. A virtual machine hypervisor enables designers to optimize performance by tweaking resource mapping even after deployment.</p></p></div><p></span></div></p><div
class="keywords"><h2>Topics covered in this article</h2><ul><li><a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#security">security</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#operating%20system">operating system</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Manycore">virtual machine monitor</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/">Virtualization</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/#hypervisor">hypervisor</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Gfx_Video">graphics</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/#virtual">virtual</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/#vmm">vmm</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Obsolescence">life-cycle</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/multicore/#across%20multiple%20cores">across multiple cores</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/#separation%20kernel">separation kernel</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#safety-critical">safety-critical</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#cyber%20attack">cyber attack</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#lynuxworks">lynuxworks</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Military">defense</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#secure">secure</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/linux/">Linux</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20os">embedded os</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#rtos">rtos</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/multicore/">multicore</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#partition">partition</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/multicore/#multicore%20platform">multicore platform</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/android/">Android</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#vxworks">vxworks</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Network%20testing">tcp</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Windows%20CE">ce</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Diagnostics">debug</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20systems">embedded systems</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#malicious%20code">malicious code</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#debug%20tools">debug tools</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Diagnostics">debugging</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#software%20analysis">software analysis</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/MATLAB">programming</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20designs">embedded designs</a></li></ul></div>]]></content:encoded>
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		<title>Don&#039;t forget the &#064;Freescale eCast at 1pm CST today &#8211; multicore with great info o&#8230;</title>
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		<pubDate>Tue, 22 Nov 2011 14:40:18 +0000</pubDate>
		<dc:creator>Multicore TechChannel</dc:creator>
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		<title>Really good eCast today from &#064;WindRiver and &#064;VDC on development challenges, mark&#8230;</title>
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		<pubDate>Thu, 17 Nov 2011 05:03:49 +0000</pubDate>
		<dc:creator>Multicore TechChannel</dc:creator>
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		<title>Techniques, tools, and tips impart design insight</title>
		<link>http://embedded-computing.com/techniques-impart-design-insight</link>
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		<pubDate>Fri, 11 Nov 2011 15:00:00 +0000</pubDate>
		<dc:creator>Warren Webb, Editorial Director</dc:creator>
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		<category><![CDATA[Tracking Trends in Embedded Technology]]></category>
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		<description><![CDATA[Editorial Director Warren Webb walks the tight rope between performance and power dissipation, a topic featured in this issue of Embedded Computing Design.]]></description>
			<content:encoded><![CDATA[<div
class="story"><span
id="more-466917"></span><span
class='body'><p
class="body-text">As embedded designers delve into each new project, the system goals invariably include increased performance, a reduced form factor, longer battery life, and silent operation. All of these goals run counter to effective <a
rel="tag" href="http://channels.opensystemsmedia.com/rugged%20computer">thermal management</a>, and designers are constantly facing the prospect of sacrificing performance in order to effectively dissipate the <a
rel="tag" href="http://channels.opensystemsmedia.com/cooling">heat</a> generated by today&#8217;s high-performance integrated circuitry.</p><p
class="body-text"><span
id="Ad-ABD-1" style="display: none; float: left;"></span>Silicon developers are attacking the problem with <a
rel="tag" href="http://tech.opensystemsmedia.com/multicore/">multicore</a><span
class="social" style="margin:0 0 0 3px">[<a
href="http://opsy.st/multicore-facebook"><img
style="margin:0 2px -2px 2px;vertical-align:baseline" src="http://i.opensystemsmedia.com/i/a-facebook-12x12.gif" /></a>]</span> architectures to boost performance with parallel processing while minimizing the increase in power dissipation. For new designs, multicore technology has become the preferred design strategy to increase performance while keeping power consumption low. In addition to providing power savings, multicore-based systems often allow designers to combine several functions into a&nbsp;single package, resulting in fewer overall components and lower recurring costs. Looking to the future, silicon developers continue to search for new techniques to extend the performance-to-power ratio. For example, at this year&#8217;s Intel Developer Forum, researchers described a near-threshold voltage concept that promises to deliver 5x the energy efficiency of current processor architectures.</p><p
class="body-text">Although new techniques and power-saving architectures are in the pipeline for future products, current designs must focus on today&#8217;s technology. In the Silicon section of this issue of <span
class="italics"><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20computing">Embedded Computing</a> Design</span>, industry experts cover methods designers can use to extract the best performance from an <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20design">embedded design</a> without crossing over into those forbidden power zones.</p><p
class="body-text">J. Scott Gardner of Advantage Engineering describes the findings of a <a
rel="tag" href="http://channels.opensystemsmedia.com/VIA%20Technologies">VIA Technologies</a> study demonstrating how adaptive <a
rel="tag" href="http://tech.opensystemsmedia.com/rugged-power/#power%20management">power management</a> can maximize performance and dynamically adjust the CPU voltage and clock rate to stay just below the thermal design power threshold. This approach helps designers bring higher-performance architectures into the embedded power envelope. In the same section, John Goodacre of <a
rel="tag" href="http://channels.opensystemsmedia.com/ARM">ARM</a> describes how processor innovation and low-power design have become the central focus of embedded design. John points out that energy efficiency is currently the primary differentiator in processing and will be the key driver for the future of computing.</p><p
class="heading-1">Detect and correct</p><p
class="body-text">With high-performance multicore processors becoming the norm in new <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20designs">embedded designs</a>, software development, <a
rel="tag" href="http://channels.opensystemsmedia.com/Diagnostics">debug</a>, and verification tasks now fall on the critical path to delivery. In the Software section of this issue, you can learn about the latest automatic analysis tools and techniques available to verify software functionality for your next embedded project.</p><p
class="body-text">In a detailed article, Marek Kucharski and Miros&#322;aw Zielinski of Parasoft describe how verification techniques such as pattern-based static code analysis, runtime memory monitoring, unit testing, and flow analysis can be combined to locate bugs in embedded C software. Presenting a different approach to system verification and validation, Guido Sandmann, Joachim Schlosser, and Brett&nbsp;Murphy of MathWorks detail the benefits of <a
rel="tag" href="http://channels.opensystemsmedia.com/Model">Model-Based Design</a>. This method allows design teams to find hardware and software errors earlier in the design cycle through operational simulation and <a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/#virtual">virtual</a> test suites. For <a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#safety-critical">safety-critical</a> applications, the software certification process requires proof that software testing provides complete source code coverage. AdaCore&#8217;s Benjamin&nbsp;Brosgol presents an open coverage analysis platform for verification of safety-critical software written in the Ada language.</p><p
class="heading-1">Safe and <a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#secure">secure</a></p><p
class="body-text">Real-time connectivity and remote deployment have become common requirements for the latest generation of embedded devices. While these requirements enable new and unique performance capabilities, they also expose the system to increased <a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#security">security</a> risks.</p><p
class="body-text">In this issue&#8217;s Strategies section, Andy Bochman and Irv Badr of IBM Rational discuss the cyber security assessment necessary when deploying software-based systems for the <a
rel="tag" href="http://tech.opensystemsmedia.com/smart-energy/#smart%20grid">smart grid</a>. The article outlines new <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#software%20security">software security</a> controls and policies needed for these potentially exposed and vulnerable systems. Expanding on the security topic, J. Ryan Kenny of QuantumTrace demonstrates the problems and challenges encountered when developing, certifying, and implementing security features in embedded architectures. Ryan also describes the details of three security testing attributes that are widely practiced in the verification of <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20system">embedded system</a> code: authentication, command integrity, and security logs.</p><p
class="body-text">I hope you find the articles and technical details on power, performance, security, and software verification presented in this issue of <span
class="italics">Embedded Computing Design</span> helpful in your search for embedded design insight and shortcuts. As we approach a new year, we will make every effort to bring you design information that is pertinent and on the cutting edge of embedded development. If you have ideas for future articles and coverage that would help in your design efforts, please let us know. Also, if you would like to write a technical article or produce an information <a
rel="tag" href="http://channels.opensystemsmedia.com/Video">video</a> that would be of interest to other designers, please send me an e-mail with a short abstract.</p></p></div><p></span></div></p><div
class="keywords"><h2>Topics covered in this article</h2><ul><li><a
rel="tag" href="http://channels.opensystemsmedia.com/rugged%20computer">thermal management</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/cooling">heat</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/multicore/">multicore</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20computing">embedded computing</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20design">embedded design</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/VIA%20Technologies">VIA Technologies</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/rugged-power/#power%20management">power management</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/ARM">arm</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20designs">embedded designs</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Diagnostics">debug</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Model">Model-based design</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#safety-critical">safety-critical</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/#virtual">virtual</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#secure">secure</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#security">security</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#software%20security">software security</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20system">embedded system</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/smart-energy/#smart%20grid">smart grid</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Video">video</a></li></ul></div>]]></content:encoded>
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		<title>Alcatel Lucent talked about a new 400 Gb/s NPU: http://ow.ly/7d2Oa</title>
		<link>http://www.facebook.com/MulticoreTech/posts/284547718242513</link>
		<comments>http://www.facebook.com/MulticoreTech/posts/284547718242513#comments</comments>
		<pubDate>Sat, 29 Oct 2011 22:09:25 +0000</pubDate>
		<dc:creator>Multicore TechChannel</dc:creator>
				<category><![CDATA[Blog]]></category>

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		<description><![CDATA[Alcatel Lucent talked about a new 400 Gb/s NPU: http://ow.ly/7d2OaNew DNA for the Evolution of Service Routingow.lyNext Generation Communications by Alcatel-Lucent. Transforming communications for a world that is always on.]]></description>
			<content:encoded><![CDATA[Alcatel Lucent talked about a new 400 Gb/s NPU: <a href="http://ow.ly/7d2Oa"  rel="nofollow nofollow" onmousedown="UntrustedLink.bootstrap($(this), &quot;oAQFBCq3-&quot;, event, bagof(&#123;&#125;));">http://ow.ly/7d2Oa</a><br/><br/><a href="http://ow.ly/7d2Oa" id="" title=""  onclick="" style="" onmousedown="UntrustedLink.bootstrap($(this), &quot;1AQE07mq2&quot;, event, bagof(&#123;&#125;));" rel="nofollow"><img class="img" src="http://platform.ak.fbcdn.net/www/app_full_proxy.php?app=183319479511&amp;v=1&amp;size=z&amp;cksum=9cffcad217be3ccdc29772d4f2abcc85&amp;src=http%3A%2F%2Fimages.tmcnet.com%2Fonline-communities%2Fnext-generation-communications%2Fimages%2Falu-ngc-blog-banner.gif" alt="" /></a><br/><a href="http://ow.ly/7d2Oa" id=""  style="" onmousedown="UntrustedLink.bootstrap($(this), &quot;3AQGR4C1O&quot;, event, bagof(&#123;&#125;));" rel="nofollow">New DNA for the Evolution of Service Routing</a><br/>ow.ly<br/>Next Generation Communications by Alcatel-Lucent. Transforming communications for a world that is always on.]]></content:encoded>
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		<title>For multicore systems, a better Task Manager in Windows 8</title>
		<link>http://www.facebook.com/MulticoreTech/posts/280178132016702</link>
		<comments>http://www.facebook.com/MulticoreTech/posts/280178132016702#comments</comments>
		<pubDate>Fri, 28 Oct 2011 20:59:33 +0000</pubDate>
		<dc:creator>Multicore TechChannel</dc:creator>
				<category><![CDATA[Blog]]></category>

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		<description><![CDATA[For multicore systems, a better Task Manager in Windows 8Windows 8: a task manager for multicore systemsus.generation-nt.comThe Windows 8 task manager will allow you to better view a multicore systems performance, with up to 640 logical processors supp...]]></description>
			<content:encoded><![CDATA[For multicore systems, a better Task Manager in Windows 8<br/><br/><a href="http://us.generation-nt.com/windows-8-task-manager-multicore-news-3216761.html" id="" title=""  onclick="" style="" onmousedown="UntrustedLink.bootstrap($(this), &quot;OAQHpDiKi&quot;, event, bagof(&#123;&#125;));" rel="nofollow"><img class="img" src="http://external.ak.fbcdn.net/safe_image.php?d=AQD2dn5r71RfmckI&amp;w=90&amp;h=90&amp;url=http%3A%2F%2Fimg-us2.generation-nt.com%2Fwindows-8-historique-usage-cpu-infobulle_00FA000001162841.jpg" alt="" /></a><br/><a href="http://us.generation-nt.com/windows-8-task-manager-multicore-news-3216761.html" id=""  style="" onmousedown="UntrustedLink.bootstrap($(this), &quot;IAQEMX0Q3&quot;, event, bagof(&#123;&#125;));" rel="nofollow">Windows 8: a task manager for multicore systems</a><br/>us.generation-nt.com<br/>The Windows 8 task manager will allow you to better view a multicore systems performance, with up to 640 logical processors supported.]]></content:encoded>
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		</item>
		<item>
		<title>Required viewing for anyone doing multicore development. Excellent information o&#8230;</title>
		<link>http://www.facebook.com/MulticoreTech/posts/280864201944198</link>
		<comments>http://www.facebook.com/MulticoreTech/posts/280864201944198#comments</comments>
		<pubDate>Fri, 21 Oct 2011 19:44:37 +0000</pubDate>
		<dc:creator>Multicore TechChannel</dc:creator>
				<category><![CDATA[Blog]]></category>

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		<description><![CDATA[Required viewing for anyone doing multicore development. Excellent information on SW dev for multicore: http://ow.ly/757h1]]></description>
			<content:encoded><![CDATA[Required viewing for anyone doing multicore development. Excellent information on SW dev for multicore: <a href="http://ow.ly/757h1"  rel="nofollow nofollow" onmousedown="UntrustedLink.bootstrap($(this), &quot;bAQHmFevs&quot;, event, bagof(&#123;&#125;));">http://ow.ly/757h1</a>]]></content:encoded>
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		<item>
		<title>Don&#039;t forget the multicore virtual event today &#8211; untangling multicore event, tal&#8230;</title>
		<link>http://www.facebook.com/MulticoreTech/posts/280258575338094</link>
		<comments>http://www.facebook.com/MulticoreTech/posts/280258575338094#comments</comments>
		<pubDate>Thu, 20 Oct 2011 15:41:47 +0000</pubDate>
		<dc:creator>Multicore TechChannel</dc:creator>
				<category><![CDATA[Blog]]></category>

		<guid isPermaLink="false">http://tech.opensystemsmedia.com/multicore/?guid=fcf66b5d9a16c5407c9bd30292611ffe</guid>
		<description><![CDATA[Don&#039;t forget the multicore virtual event today - untangling multicore event, talk on analysis tools, dev tools, and EEMBC membership http://ow.ly/73yl0Broadcast Schedule  –  OpenSystems Mediaow.lyE-casts cover a variety of informative topics, fe...]]></description>
			<content:encoded><![CDATA[Don&#039;t forget the multicore virtual event today - untangling multicore event, talk on analysis tools, dev tools, and EEMBC membership <a href="http://ow.ly/73yl0"  rel="nofollow nofollow" onmousedown="UntrustedLink.bootstrap($(this), &quot;UAQHlKPvd&quot;, event, bagof(&#123;&#125;));">http://ow.ly/73yl0</a><br/><br/><br/><a href="http://ow.ly/73yl0" id=""  style="" onmousedown="UntrustedLink.bootstrap($(this), &quot;eAQEcUbFa&quot;, event, bagof(&#123;&#125;));" rel="nofollow">Broadcast Schedule  –  OpenSystems Media</a><br/>ow.ly<br/>E-casts cover a variety of informative topics, featuring experts from industry leading companies presenting along with moderators from our...]]></content:encoded>
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		<title>Multicore TechChannel&#8217;s Facebook Wall 2011-10-19 09:50:38</title>
		<link>http://www.facebook.com/MulticoreTech/posts/234668053253689</link>
		<comments>http://www.facebook.com/MulticoreTech/posts/234668053253689#comments</comments>
		<pubDate>Wed, 19 Oct 2011 16:50:38 +0000</pubDate>
		<dc:creator>Multicore TechChannel</dc:creator>
				<category><![CDATA[Blog]]></category>

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		<description><![CDATA[Multicore TechChanneltech.opensystemsmedia.comEver-smaller silicon geometries are reaching their physical limits. This threatens to slow the pace of Moore’s Law to a stand-still. As a result, multicore technology is becoming widely available to addre...]]></description>
			<content:encoded><![CDATA[<br/><a href="http://tech.opensystemsmedia.com/multicore/2011/10/#.Tp7_z9FQEH8.facebook" id=""  style="" onmousedown="UntrustedLink.bootstrap($(this), &quot;cAQENxjG3&quot;, event, bagof(&#123;&#125;));" rel="nofollow">Multicore TechChannel</a><br/>tech.opensystemsmedia.com<br/>Ever-smaller silicon geometries are reaching their physical limits. This threatens to slow the pace of Moore’s Law to a stand-still. As a result, multicore technology is becoming widely available to address the performance bottleneck. The key to successful multicore product development is system and...]]></content:encoded>
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		<title>Make sure to attend the OSM Multicore Virtual Event Sessions Oct 19th &#8211; lots of&#8230;</title>
		<link>http://www.facebook.com/MulticoreTech/posts/278403468856938</link>
		<comments>http://www.facebook.com/MulticoreTech/posts/278403468856938#comments</comments>
		<pubDate>Sun, 16 Oct 2011 15:39:55 +0000</pubDate>
		<dc:creator>Multicore TechChannel</dc:creator>
				<category><![CDATA[Blog]]></category>

		<guid isPermaLink="false">http://tech.opensystemsmedia.com/multicore/?guid=18897ac04b75ceb72c8c95761fa009b0</guid>
		<description><![CDATA[Make sure to attend the OSM Multicore Virtual Event Sessions Oct 19th - lots of great HW, SW, tools information from experts. Sign up here: http://ow.ly/6YNA7http://ow.ly/6YNA7ow.ly]]></description>
			<content:encoded><![CDATA[Make sure to attend the OSM Multicore Virtual Event Sessions Oct 19th - lots of great HW, SW, tools information from experts. Sign up here: <a href="http://ow.ly/6YNA7"  rel="nofollow nofollow" onmousedown="UntrustedLink.bootstrap($(this), &quot;iAQG3tgKj&quot;, event, bagof(&#123;&#125;));">http://ow.ly/6YNA7</a><br/><br/><br/><a href="http://ow.ly/6YNA7" id=""  style="" onmousedown="UntrustedLink.bootstrap($(this), &quot;IAQEMX0Q3&quot;, event, bagof(&#123;&#125;));" rel="nofollow"><a href="http://ow.ly/6YNA7"  rel="nofollow nofollow" onmousedown="UntrustedLink.bootstrap($(this), &quot;SAQFOxFeO&quot;, event, bagof(&#123;&#125;));">http://ow.ly/6YNA7</a></a><br/>ow.ly]]></content:encoded>
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		<title>Think long term on design decisions, day-to-day or app-specific</title>
		<link>http://embedded-computing.com/think-term-design-decisions-day-to-day-app-specific</link>
		<comments>http://embedded-computing.com/think-term-design-decisions-day-to-day-app-specific#comments</comments>
		<pubDate>Wed, 12 Oct 2011 15:00:00 +0000</pubDate>
		<dc:creator>Warren Webb, Editorial Director</dc:creator>
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		<description><![CDATA[Editorial Director Warren Webb's take on the importance of memory architecture selection in embedded device design and a roundup of this edition of Embedded Computing Design.]]></description>
			<content:encoded><![CDATA[<div
class="story"><span
id="more-466497"></span><span
class='body'><p
class="body-text">Although embedded devices are tailored to a wide variety of applications and environments, from portable consumer devices to critical medical or <a
rel="tag" href="http://channels.opensystemsmedia.com/Military">military</a> systems, the one design step that is universal in many of these applications is memory architecture selection. Designers must evaluate memory products based on parameters such as capacity, power, speed, size, and cost to&nbsp;meet the constant demand for improved system bandwidth and performance.</p><p
class="body-text"><span
id="Ad-ABD-1" style="display: none; float: left;"></span>Because of the extended life expectancy of some embedded devices, designers might also need to examine <a
rel="tag" href="http://channels.opensystemsmedia.com/Obsolescence">life-cycle</a> ratings and the prospects for long-term availability. With plug-in modules now common in many embedded devices, designers must choose a memory technology standard with similar extended availability. Many <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20designs">embedded designs</a> such as safety- and <a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#security-critical">security-critical</a> <a
rel="tag" href="http://channels.opensystemsmedia.com/Military">military applications</a> must also provide memory protection to guard against data corruption or <a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#theft">theft</a>.</p><p
class="body-text">In this issue of <span
class="italics"><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20computing">Embedded Computing</a> Design</span>, we present a broad slice of embedded technology including a detailed discussion on memory selection. Paul Plitzuweit of Datakey Electronics headlines the Silicon section as he examines the two major memory options for embedded designs, including consumer devices like SD cards and USB flash drives or OEM-focused products with <a
rel="tag" href="http://channels.opensystemsmedia.com/Military">rugged</a> construction, <a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#secure">secure</a> form factors, and long-term availability. Paul&#8217;s detailed rundown on the pros and cons of specific memory architectures in diverse applications is a must-read if you are embarking on a new embedded project.</p><p
class="body-text">In addition to memory architecture decisions, <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20design">embedded design</a> teams face an even larger group of options when selecting the software system that can meet the design goals and performance requirements for each new project. Open-source code, a modular architecture and extensive feature set, plus a worldwide army of developers make <a
rel="tag" href="http://tech.opensystemsmedia.com/linux/">Linux</a><span
class="social" style="margin:0 0 0 3px">[<a
href="http://opsy.st/linux-facebook"><img
style="margin:0 2px -2px 2px;vertical-align:baseline" src="http://i.opensystemsmedia.com/i/a-facebook-12x12.gif" /></a>]</span> a formidable contender for many new embedded projects. In our Software section, MontaVista Software&#8217;s Jim Ready and Patrick MacCartee demonstrate techniques for using Linux-based <a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/">virtualization</a><span
class="social" style="margin:0 0 0 3px">[<a
href="http://opsy.st/virtualization-facebook"><img
style="margin:0 2px -2px 2px;vertical-align:baseline" src="http://i.opensystemsmedia.com/i/a-facebook-12x12.gif" /></a>]</span> methodologies to maximize the high-level performance requirements of <a
rel="tag" href="http://tech.opensystemsmedia.com/multicore/">multicore</a><span
class="social" style="margin:0 0 0 3px">[<a
href="http://opsy.st/multicore-facebook"><img
style="margin:0 2px -2px 2px;vertical-align:baseline" src="http://i.opensystemsmedia.com/i/a-facebook-12x12.gif" /></a>]</span> designs while avoiding increases in cost or complexity. The authors illustrate the characteristics of multiple embedded virtualization technologies and dispel a widely held misconception regarding <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#operating%20system">operating system</a> combinations in multicore applications.</p><p
class="body-text">Although memory and software selection tasks are part of every embedded project, the decisions become much more wide-ranging as the conversation turns to specific vertical markets. In this issue, market experts answer both policy and technical questions about the current state of In-<a
rel="tag" href="http://channels.opensystemsmedia.com/Automotive">Vehicle</a> Infotainment (IVI) applications and the changes we can expect going forward. These IVI systems combine a variety of hardware, software, and communications components to provide features such as hands-free communications, voice-activated music selection, real-time navigation/traffic information, plus streaming multimedia and interactive gaming for passengers. As consumers demand ever-present connectivity, vehicle computers and infotainment systems have become the next embedded design challenge.</p><p
class="body-text">Seamless connectivity is a very important aspect of embedded <a
rel="tag" href="http://channels.opensystemsmedia.com/Automotive">automotive</a> electronics. For example, consumers expect automatic data links to be established between IVI systems and portable computing, cellular, or entertainment devices when within range. IVI systems create a unique challenge for developers because consumers always want the latest technology but may keep the same <a
rel="tag" href="http://channels.opensystemsmedia.com/Automotive">automobile</a> for years.</p><p
class="body-text">Joel Andrew Hoffmann, board director of the GENIVI Alliance and business analyst for Intel&#8217;s Automotive Solutions Division, starts this issue&#8217;s Strategies section by discussing the latest IVI technologies and what advancements we can expect in the near future. Joel also explains the GENIVI Alliance open-source <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#middleware">middleware</a> compliance program aimed at eliminating fragmentation within the industry for IVI product developers. Also in the Strategies section, Andy Gryc of QNX Software Systems and Paul Sykes of Freescale Semiconductor describe their companies&#8217; strategic partnership and outline upcoming challenges in automobile infotainment development. Along with providing techniques to support fast and reliable IVI system updates, Andy and Paul show how scalable multicore CPU architectures can simplify the design process. To wrap up our discussion on IVI, Pierre Teyssier of Sierra <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-wireless/#wireless">Wireless</a> points out the performance and usability advantages of deploying Long-Term Evolution (<a
rel="tag" href="http://tech.opensystemsmedia.com/lte-advanced/#lte">LTE</a>) technology in IVI systems, as well as its accompanying design challenges such as complex network handoffs and <a
rel="tag" href="http://channels.opensystemsmedia.com/communications%20tech">antenna</a> requirements. Pierre emphasizes that designers using LTE need to choose adaptable platforms that allow new capabilities to be added over time via software updates.</p><p
class="body-text">The technical articles and Q&amp;As in this issue delve into some of the hardware and software development details related to almost every design project, plus the problems and challenges you might expect in a relatively new market such as vehicle infotainment systems. Our job here at <span
class="italics">Embedded Computing Design</span> is to bring you the latest trends and technology updates to keep you ahead of the competition. Please give us your ideas on print articles and online updates that we can provide to support your design efforts. If you have a suggestion for a technical article or <a
rel="tag" href="http://channels.opensystemsmedia.com/Video">video</a> that would be of interest to you or other designers, please let me know.</p></p></div><p></span></div></p><div
class="keywords"><h2>Topics covered in this article</h2><ul><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Military">military</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Military">Military applications</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#security-critical">security-critical</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20designs">embedded designs</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Obsolescence">life-cycle</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#theft">theft</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20computing">embedded computing</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Military">rugged</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#secure">secure</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#operating%20system">operating system</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20design">embedded design</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/">Virtualization</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/multicore/">multicore</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/linux/">Linux</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Automotive">vehicle</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Automotive">automobile</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Automotive">automotive</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#middleware">middleware</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-wireless/#wireless">wireless</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/communications%20tech">antenna</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/lte-advanced/#lte">lte</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Video">video</a></li></ul></div>]]></content:encoded>
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		</item>
		<item>
		<title>Bridge joins interconnect protocols</title>
		<link>http://embedded-computing.com/bridge-joins-interconnect-protocols</link>
		<comments>http://embedded-computing.com/bridge-joins-interconnect-protocols#comments</comments>
		<pubDate>Sat, 01 Oct 2011 00:00:00 +0000</pubDate>
		<dc:creator>Warren Webb, Editorial Director</dc:creator>
				<category><![CDATA[Blog]]></category>
		<category><![CDATA[Columns]]></category>
		<category><![CDATA[Products]]></category>
		<category><![CDATA[2011 ECD Oct]]></category>
		<category><![CDATA[Editor's Choice]]></category>
		<category><![CDATA[Integrated Device Technology]]></category>

		<guid isPermaLink="false">http://tech.opensystemsmedia.com/multicore/?guid=c3560cb27c26a3fab1660cc71e9e37ca</guid>
		<description><![CDATA[As embedded designers start each new project, they face the potential challenge of matching the latest high-performance computing devices with legacy peripherals. Targeting these challenges, Integrated Device Technology (IDT) recently announced a protocol-conversion bridge allowing designe...]]></description>
			<content:encoded><![CDATA[<p><img
width='197' align='right' border='0' src='http://i.opensystemsmedia.com/?w=250&#038;q=89&#038;src=http%3A%2F%2Fosmproductphotos.s3.amazonaws.com%2F52449.jpg'>As embedded designers start each new project, they face the potential challenge of matching the latest high-performance computing devices with legacy peripherals. Targeting these challenges, Integrated Device Technology (IDT) recently announced a protocol-conversion bridge allowing designers to connect the latest x86 processor technology with existing <a
rel="tag" href="http://channels.opensystemsmedia.com/Backplane">backplane</a> interconnect technologies.</p><p>The IDT Tsi721 is a PCI Express-to-<a
rel="tag" href="http://channels.opensystemsmedia.com/RapidIO">RapidIO</a> bridge that allows existing systems in the <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-wireless/#wireless">wireless</a>, <a
rel="tag" href="http://channels.opensystemsmedia.com/Military">defense</a>, <a
rel="tag" href="http://channels.opensystemsmedia.com/Gfx_Video">imaging</a>, and industrial markets to maintain their high-performance, low-latency, and highflexibility characteristics with Intel&#8217;s latest PCI Express-based architecture. Conversely, the enterprise <a
rel="tag" href="http://tech.opensystemsmedia.com/cloud/">cloud</a><span
class="social" style="margin:0 0 0 3px">[<a
href="http://opsy.st/cloud-facebook"><img
style="margin:0 2px -2px 2px;vertical-align:baseline" src="http://i.opensystemsmedia.com/i/a-facebook-12x12.gif" /></a>]</span> computing and server markets that already use PCI Express-enabled processors can now take advantage of RapidIO as a backplane interconnect. The IDT Tsi721 offers eight direct memory access and four messaging engines, each capable of transferring data and operating at line speeds of 16 Gbps. This simplifies system-level software development by enabling the allocation of multiple engines per core in a <a
rel="tag" href="http://tech.opensystemsmedia.com/multicore/">multicore</a><span
class="social" style="margin:0 0 0 3px">[<a
href="http://opsy.st/multicore-facebook"><img
style="margin:0 2px -2px 2px;vertical-align:baseline" src="http://i.opensystemsmedia.com/i/a-facebook-12x12.gif" /></a>]</span>, multithreaded system. The IDT Tsi721 is available in a 13 mm x 13 mm FCBGA package and is priced at $49 each in volume. IDT offers Tsi721 software support for <a
rel="tag" href="http://tech.opensystemsmedia.com/linux/">Linux</a><span
class="social" style="margin:0 0 0 3px">[<a
href="http://opsy.st/linux-facebook"><img
style="margin:0 2px -2px 2px;vertical-align:baseline" src="http://i.opensystemsmedia.com/i/a-facebook-12x12.gif" /></a>]</span> and Windows.</p></p><div
class="keywords"><h2>Topics covered in this article</h2><ul><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Backplane">backplane</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/multicore/">multicore</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-wireless/#wireless">wireless</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/RapidIO">RapidIO</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Gfx_Video">imaging</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Military">defense</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/cloud/">Cloud</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/linux/">Linux</a></li></ul></div>]]></content:encoded>
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		<title>Roving Reporter: Breaking Networking Performance Barriers with Multi-core Packet Acceleration</title>
		<link>http://embedded-computing.com/roving-barriers-multi-core-packet-acceleration</link>
		<comments>http://embedded-computing.com/roving-barriers-multi-core-packet-acceleration#comments</comments>
		<pubDate>Wed, 21 Sep 2011 20:52:30 +0000</pubDate>
		<dc:creator>Warren Webb, Editorial Director</dc:creator>
				<category><![CDATA[Blog]]></category>
		<category><![CDATA[Columns]]></category>

		<guid isPermaLink="false">http://embedded.communities.intel.com/community/en/applications/blog/2011/09/21/roving-reporter-breaking-networking-performance-barriers-with-multi-core-packet-acceleration</guid>
		<description><![CDATA[<div><p>Telecom infrastructure networks are experiencing dramatic increases in data traffic, largely driven by multimedia content from wireless and wired devices. This growth is challenging service providers to meet network performance demands while growing their average revenue per user. From the hardware perspective, the latest Intel Xeon&#174; processors provide the efficient performance needed to deal with new demands while allowing network equipment manufacturers to consolidate application, control, and packet processing on the same platform for a more efficient solution.&#160; Although traditional software solutions have not been optimized for network performance, telecom equipment providers must find new techniques to combine operating systems, networking software and multi-core silicon to address business and performance challenges in today&#8217;s highly competitive market.</p><p>&#160;</p><p>Offering a software solution for network workload consolidation, <a rel="nofollow" target="_blank" href="http://www.windriver.com/">Wind River</a> recently announced a networking acceleration stack for Linux and VxWorks aimed at accelerating IP packet forwarding on carrier-grade telecommunications equipment. The <a rel="nofollow" target="_blank" href="http://www.windriver.com/products/platforms/network-acceleration/">Wind River Network Acceleration Platform</a> manages processing operations over multiple cores to accelerate control and data plane activities and deliver multiple gigabit Ethernet wire-speed performance (See figure 1). By adopting the multi-core asymmetric multiprocessing (AMP) approach the Network Acceleration Platform enhances the standard Linux networking stack to support high-performance network acceleration capabilities exceeding what is possible using symmetric multiprocessing (SMP) mode alone. Offering 10 times the performance of standard Linux configurations, Wind River Network Acceleration Platform helps eliminate bottlenecks not only in moving packets through the silicon itself, but throughout the entire networking platform. The latest release expands hardware support for the Intel Xeon next-generation multicore processors and allows network performance to scale efficiently with the number of cores in a processor. In addition, Wind River is providing Network Acceleration developers with multi-core enabled development, testing, debugging, and simulation tools required to simulate and test systems in complex multi-core environments.</p><p>&#160;</p><p><a rel="nofollow" target="_blank" href="http://embedded.communities.intel.com/servlet/JiveServlet/showImage/38-5241-2887/windriver_netacceleration_arch.jpg"><img alt="windriver_netacceleration_arch.jpg" class="jive-image-thumbnail jive-image" height="166" src="http://embedded.communities.intel.com/servlet/JiveServlet/downloadImage/38-5241-2887/450-166/windriver_netacceleration_arch.jpg" width="450" /></a></p><p>&#160;</p><p>Extending packet processing performance, Intel recently announced its 32nm-fabricated Xeon&#174; 5600 processors as the next generation upgrade to the Xeon&#174; 5500 family. In addition to several enterprise-class versions of the Xeon&#174; 5600, Intel introduced four models with seven-year lifecycle support for embedded applications. The 2.4GHz, 80 Watt Xeon&#174; E5645 and the 2.0GHz, 60 Watt Xeon&#174; L5638 each provide six cores and 12 threads. There are two quad-core embedded versions including the 4GHz, 80 Watt Xeon&#174; E5620 and the 1.86GHz, 40 Watt Xeon&#174; L5618. The Intel Xeon&#174; processor 5600 series includes <a rel="nofollow" target="_blank" href="http://www.intel.com/content/www/us/en/architecture-and-technology/advanced-encryption-standard--aes-/data-protection-aes-general-technology.html">Intel&#174; AES New Instructions</a> (Intel&#174; AES-NI), improving performance for disk and database encryption plus secure Internet transactions. The processors also feature <a rel="nofollow" target="_blank" href="http://www.intel.com/technology/virtualization/technology.htm?iid=tech_vt+tech">Intel&#174; Virtualization Technology</a> for flexible virtualization, <a rel="nofollow" target="_blank" href="http://www.intel.com/content/www/us/en/io/quickpath-technology/quickpath-technology-general.html">Intel&#174; QuickPath Technology</a> to maximize multi-core performance, plus <a rel="nofollow" target="_blank" href="http://www.intel.com/content/www/us/en/architecture-and-technology/hyper-threading/hyper-threading-technology.html">Intel&#174; Hyper-Threading Technology</a> to deliver top performance for bandwidth-intensive applications.</p><p>&#160;</p><p><a rel="nofollow" target="_blank" href="http://www.6wind.com/products-services/6windgate-software">6WINDGate</a> from <a rel="nofollow" target="_blank" href="http://www.6wind.com/">6WIND</a> is another software solution that provides packet processing optimization for networking equipment, wireless infrastructure, security appliances and data centers (See figure 2). The software provides up to ten times the packet processing performance of a standard networking stack and significantly improves the price-performance and power-performance ratios of networking equipment. 6WINDGate is compatible with standard operating system APIs to ensure that clients can migrate either from a single-core to a multi-core platform, or from one multi-core platform to another, without needing to rewrite their existing software.&#160; On a dual-core Intel&#174; Xeon&#174; processor E5645 platform with a clock speed of 3.33GHz, 6WINDGate delivers over 16 million packets per second, per core of IP forwarding performance, thereby forwarding 10Gbps of network traffic in each core. This performance scales linearly with the number of cores configured to run 6WINDGate until the maximum bandwidth of the hardware platform is reached. Processor cores not used to run 6WINDGate are available to run value-added application software or Virtual Machines (VMs), resulting in an efficient and flexible system for advanced networking equipment.</p><p>&#160;</p><p><a rel="nofollow" target="_blank" href="http://embedded.communities.intel.com/servlet/JiveServlet/showImage/38-5241-2888/Software-architecture-for-website.jpg"><img alt="Software-architecture-for-website.jpg" class="jive-image" height="293" src="http://embedded.communities.intel.com/servlet/JiveServlet/downloadImage/38-5241-2888/300-293/Software-architecture-for-website.jpg" width="300" /></a></p><p>&#160;</p><p>Providing off-the-shelf hardware to support the transition to integrated network workloads, <a rel="nofollow" target="_blank" href="http://www.emersonnetworkpower.com/en-US/Pages/Default.aspx">Emerson Network Power</a> recently introduced a new <a rel="nofollow" target="_blank" href="http://www.picmg.org/v2internal/resourcepage2.cfm?id=2">AdvancedTCA</a> server blade featuring a six-core processor from the Intel&#174; Xeon&#174; processor 5600 series to deliver optimized virtualization and power management. The dual-processor ATCA-7365 is the company&#8217;s highest-performance 10Gbps ATCA server blade to date and supports up to 96GB DDR3 memory (See figure 3).&#160; Designed to enable network and service providers to lower their capital and operating expenses, the off-the-shelf ATCA-7365 supports a broad array of communications applications that require high network throughput such as telecom. The ATCA-7365 is available with a variety of rear transition module (RTM) variants to support different I/O configurations and can be configured with a variety of software offerings including Red Hat Enterprise Linux 5.4, Wind River Platform for Network Equipment Linux Edition 3.0 and Microsoft Windows Server 2008.</p><p>&#160;</p><p><a rel="nofollow" target="_blank" href="http://embedded.communities.intel.com/servlet/JiveServlet/showImage/38-5241-2889/ATCA7365.jpg"><img alt="ATCA7365.jpg" class="jive-image-thumbnail jive-image" height="363" src="http://embedded.communities.intel.com/servlet/JiveServlet/downloadImage/38-5241-2889/450-363/ATCA7365.jpg" width="450" /></a></p><p>&#160;</p><p>With new software solutions to complement the latest Xeon processors, telecom equipment system providers have fresh options to consolidate processing workloads and improve network infrastructure performance. You can find more information and technical articles on Intel network acceleration architecture at the <a rel="nofollow" target="_blank" href="http://www.intel.com/p/en_US/embedded/hwsw/hardware/xeon">Intel&#174; Embedded Community page on Xeon processors</a>.&#160; If you are starting a new telecom or packet acceleration project with and you have questions, please share your concerns with fellow followers of the <a rel="nofollow" target="_blank" href="http://community.edc.intel.com/">Intel&#174; Embedded Community</a>. You can also keep up with the latest technical details and product announcements at the Embedded Computing Design archives on <a rel="nofollow" target="_blank" href="http://embedded-computing.com/?s=multi+core+packet+acceleration">Multi-core Packet Acceleration</a>.</p><p>&#160;</p><p>To view other community content on workload consolidation, see &#8220;<a rel="nofollow" target="_blank" href="http://embedded.communities.intel.com/docs/DOC-6849">Workload Consolidation - Top Picks</a>&#8221;</p><p><a rel="nofollow" target="_blank" href="http://embedded.communities.intel.com/servlet/JiveServlet/showImage/38-5241-2890/workload_consolidation.jpg"><img alt="workload_consolidation.jpg" class="jive-image" height="29" src="http://embedded.communities.intel.com/servlet/JiveServlet/downloadImage/38-5241-2890/48-29/workload_consolidation.jpg" width="48" /></a></p><p>Warren Webb<br />OpenSystems Media&#174;, by special arrangement with Intel&#174; Embedded Alliance</p><p>&#160;</p><p><em>Emerson Network Power is a Premier member </em><em>of the by Intel&#174; Embedded Alliance. </em><em>Wind River Systems is an Associate </em><em>member and 6WIND is an Affiliate member of the Alliance.</em></p></div>]]></description>
			<content:encoded><![CDATA[<div
class="jive-rendered-content"><p>Telecom infrastructure networks are experiencing dramatic increases in data traffic, largely driven by multimedia content from <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-wireless/#wireless">wireless</a> and wired devices. This growth is challenging service providers to meet network performance demands while growing their average revenue per user. From the hardware perspective, the latest Intel Xeon&#174; processors provide the efficient performance needed to deal with new demands while allowing network equipment manufacturers to consolidate application, control, and packet processing on the same platform for a more efficient solution.&#160; Although traditional software solutions have not been optimized for network performance, telecom equipment providers must find new techniques to combine <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#operating%20systems">operating systems</a>, networking software and multi-core silicon to address business and performance challenges in today&rsquo;s highly competitive market.</p><p
style="min-height:8pt;height:8pt;padding:0px;">&#160;</p><p>Offering a software solution for network workload consolidation, <a
rel="nofollow" class="jive-link-external-small"  href="http://www.windriver.com/">Wind River</a> recently announced a networking acceleration stack for <a
rel="tag" href="http://tech.opensystemsmedia.com/linux/">Linux</a><span
class="social" style="margin:0 0 0 3px">[<a
href="http://opsy.st/linux-facebook"><img
style="margin:0 2px -2px 2px;vertical-align:baseline" src="http://i.opensystemsmedia.com/i/a-facebook-12x12.gif" /></a>]</span> and <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#vxworks">VxWorks</a> aimed at accelerating IP packet forwarding on carrier-grade telecommunications equipment. The <a
rel="nofollow" class="jive-link-external-small"  href="http://www.windriver.com/products/platforms/network-acceleration/">Wind River Network Acceleration Platform</a> manages processing operations over multiple cores to accelerate control and data plane activities and deliver multiple gigabit Ethernet wire-speed performance (See figure 1). By adopting the multi-core <a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/#asymmetric%20multiprocessing">asymmetric multiprocessing</a> (AMP) approach the Network Acceleration Platform enhances the standard Linux networking stack to support high-performance network acceleration capabilities exceeding what is possible using <a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/#symmetric%20multiprocessing">symmetric multiprocessing</a> (SMP) mode alone. Offering 10 times the performance of standard Linux configurations, Wind River Network Acceleration Platform helps eliminate bottlenecks not only in moving packets through the silicon itself, but throughout the entire networking platform. The latest release expands hardware support for the Intel Xeon next-generation <a
rel="tag" href="http://tech.opensystemsmedia.com/multicore/">multicore</a><span
class="social" style="margin:0 0 0 3px">[<a
href="http://opsy.st/multicore-facebook"><img
style="margin:0 2px -2px 2px;vertical-align:baseline" src="http://i.opensystemsmedia.com/i/a-facebook-12x12.gif" /></a>]</span> processors and allows network performance to scale efficiently with the number of cores in a processor. In addition, Wind River is providing Network Acceleration developers with multi-core enabled development, testing, <a
rel="tag" href="http://channels.opensystemsmedia.com/Diagnostics">debugging</a>, and simulation tools required to simulate and test systems in complex multi-core environments.</p><p
style="min-height:8pt;height:8pt;padding:0px;">&#160;</p><p><a
rel="nofollow"  href="http://embedded.communities.intel.com/servlet/JiveServlet/showImage/38-5241-2887/windriver_netacceleration_arch.jpg"><img
alt="windriver_netacceleration_arch.jpg" class="jive-image-thumbnail jive-image" height="166" src="http://embedded.communities.intel.com/servlet/JiveServlet/downloadImage/38-5241-2887/450-166/windriver_netacceleration_arch.jpg" width="450"/></a></p><p
style="min-height:8pt;height:8pt;padding:0px;">&#160;</p><p>Extending packet processing performance, Intel recently announced its 32nm-fabricated Xeon&#174; 5600 processors as the next generation upgrade to the Xeon&#174; 5500 family. In addition to several enterprise-class versions of the Xeon&#174; 5600, Intel introduced four <a
rel="tag" href="http://channels.opensystemsmedia.com/Model">models</a> with seven-year lifecycle support for embedded applications. The 2.4GHz, 80 Watt Xeon&#174; E5645 and the 2.0GHz, 60 Watt Xeon&#174; L5638 each provide six cores and 12 threads. There are two quad-core embedded versions including the 4GHz, 80 Watt Xeon&#174; E5620 and the 1.86GHz, 40 Watt Xeon&#174; L5618. The Intel Xeon&#174; processor 5600 series includes <a
rel="nofollow" class="jive-link-external-small"  href="http://www.intel.com/content/www/us/en/architecture-and-technology/advanced-encryption-standard--aes-/data-protection-aes-general-technology.html">Intel&#174; AES New Instructions</a> (Intel&#174; AES-NI), improving performance for disk and database encryption plus <a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#secure">secure</a> Internet transactions. The processors also feature <a
rel="nofollow" class="jive-link-external-small"  href="http://www.intel.com/technology/virtualization/technology.htm?iid=tech_vt+tech">Intel&#174; Virtualization Technology</a> for flexible virtualization, <a
rel="nofollow" class="jive-link-external-small"  href="http://www.intel.com/content/www/us/en/io/quickpath-technology/quickpath-technology-general.html">Intel&#174; QuickPath Technology</a> to maximize multi-core performance, plus <a
rel="nofollow" class="jive-link-external-small"  href="http://www.intel.com/content/www/us/en/architecture-and-technology/hyper-threading/hyper-threading-technology.html">Intel&#174; Hyper-Threading Technology</a> to deliver top performance for bandwidth-intensive applications.</p><p
style="min-height:8pt;height:8pt;padding:0px;">&#160;</p><p><a
rel="nofollow" class="jive-link-external-small"  href="http://www.6wind.com/products-services/6windgate-software">6WINDGate</a> from <a
rel="nofollow" class="jive-link-external-small"  href="http://www.6wind.com/">6WIND</a> is another software solution that provides packet processing optimization for networking equipment, wireless infrastructure, <a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#security">security</a> appliances and data centers (See figure 2). The software provides up to ten times the packet processing performance of a standard networking stack and significantly improves the price-performance and power-performance ratios of networking equipment. 6WINDGate is compatible with standard <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#operating%20system">operating system</a> APIs to ensure that clients can migrate either from a single-core to a multi-core platform, or from one multi-core platform to another, without needing to rewrite their existing software.&#160; On a dual-core Intel&#174; Xeon&#174; processor E5645 platform with a clock speed of 3.33GHz, 6WINDGate delivers over 16 million packets per second, per core of IP forwarding performance, thereby forwarding 10Gbps of network traffic in each core. This performance scales linearly with the number of cores configured to run 6WINDGate until the maximum bandwidth of the hardware platform is reached. Processor cores not used to run 6WINDGate are available to run value-added application software or Virtual Machines (VMs), resulting in an efficient and flexible system for advanced networking equipment.</p><p
style="min-height:8pt;height:8pt;padding:0px;">&#160;</p><p><a
rel="nofollow"  href="http://embedded.communities.intel.com/servlet/JiveServlet/showImage/38-5241-2888/Software-architecture-for-website.jpg"><img
alt="Software-architecture-for-website.jpg" class="jive-image" height="293" src="http://embedded.communities.intel.com/servlet/JiveServlet/downloadImage/38-5241-2888/300-293/Software-architecture-for-website.jpg" width="300"/></a></p><p
style="min-height:8pt;height:8pt;padding:0px;">&#160;</p><p>Providing off-the-shelf hardware to support the transition to integrated network workloads, <a
rel="nofollow" class="jive-link-external-small"  href="http://www.emersonnetworkpower.com/en-US/Pages/Default.aspx">Emerson Network Power</a> recently introduced a new <a
rel="nofollow" class="jive-link-external-small"  href="http://www.picmg.org/v2internal/resourcepage2.cfm?id=2">AdvancedTCA</a> server blade featuring a six-core processor from the Intel&#174; Xeon&#174; processor 5600 series to deliver optimized virtualization and power management. The dual-processor ATCA-7365 is the company&rsquo;s highest-performance 10Gbps ATCA server blade to date and supports up to 96GB DDR3 memory (See figure 3).&#160; Designed to enable network and service providers to lower their capital and operating expenses, the off-the-shelf ATCA-7365 supports a broad array of communications applications that require high network throughput such as telecom. The ATCA-7365 is available with a variety of rear transition module (RTM) variants to support different I/O configurations and can be configured with a variety of software offerings including <a
rel="tag" href="http://tech.opensystemsmedia.com/linux/#red%20hat">Red Hat</a> Enterprise Linux 5.4, Wind River Platform for Network Equipment Linux Edition 3.0 and Microsoft Windows Server 2008.</p><p
style="min-height:8pt;height:8pt;padding:0px;">&#160;</p><p><a
rel="nofollow"  href="http://embedded.communities.intel.com/servlet/JiveServlet/showImage/38-5241-2889/ATCA7365.jpg"><img
alt="ATCA7365.jpg" class="jive-image-thumbnail jive-image" height="363" src="http://embedded.communities.intel.com/servlet/JiveServlet/downloadImage/38-5241-2889/450-363/ATCA7365.jpg" width="450"/></a></p><p
style="min-height:8pt;height:8pt;padding:0px;">&#160;</p><p>With new software solutions to complement the latest Xeon processors, telecom equipment system providers have fresh options to consolidate processing workloads and improve network infrastructure performance. You can find more information and technical articles on Intel network acceleration architecture at the <a
rel="nofollow" class="jive-link-external-small"  href="http://www.intel.com/p/en_US/embedded/hwsw/hardware/xeon">Intel&#174; Embedded Community page on Xeon processors</a>.&#160; If you are starting a new telecom or packet acceleration project with and you have questions, please share your concerns with fellow followers of the <a
rel="nofollow" class="jive-link-external-small"  href="http://community.edc.intel.com/">Intel&#174; Embedded Community</a>. You can also keep up with the latest technical details and product announcements at the Embedded Computing Design archives on <a
rel="nofollow" class="jive-link-external-small"  href="http://embedded-computing.com/?s=multi+core+packet+acceleration">Multi-core Packet Acceleration</a>.</p><p
style="min-height:8pt;height:8pt;padding:0px;">&#160;</p><p>To view other community content on workload consolidation, see &ldquo;<a
rel="nofollow" class=""  href="http://embedded.communities.intel.com/docs/DOC-6849">Workload Consolidation &#8211; Top Picks</a>&#8221;</p><p><a
rel="nofollow"  href="http://embedded.communities.intel.com/servlet/JiveServlet/showImage/38-5241-2890/workload_consolidation.jpg"><img
alt="workload_consolidation.jpg" class="jive-image" height="29" src="http://embedded.communities.intel.com/servlet/JiveServlet/downloadImage/38-5241-2890/48-29/workload_consolidation.jpg" width="48"/></a></p><p>Warren Webb<br/>OpenSystems Media&#174;, by special arrangement with Intel&#174; Embedded Alliance</p><p
style="min-height:8pt;height:8pt;padding:0px;">&#160;</p><p><em
style="">Emerson Network Power is a Premier member </em><em>of the by Intel&#174; Embedded Alliance. </em><em
style="">Wind River Systems is an Associate </em><em>member and 6WIND is an Affiliate member of the Alliance.</em></p></div></p><div
class="keywords"><h2>Topics covered in this article</h2><ul><li><a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/#asymmetric%20multiprocessing">asymmetric multiprocessing</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/#symmetric%20multiprocessing">symmetric multiprocessing</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#operating%20systems">operating systems</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#operating%20system">operating system</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/multicore/">multicore</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Diagnostics">debugging</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-wireless/#wireless">wireless</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#security">security</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/linux/#red%20hat">red hat</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#vxworks">vxworks</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Model">models</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#secure">secure</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/linux/">Linux</a></li></ul></div> <script type="text/javascript">var found_terms = new Array("asymmetric multiprocessing","symmetric multiprocessing","operating systems","operating system","multicore","debugging","wireless","security","red hat","vxworks","models","secure","Linux");</script> ]]></content:encoded>
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		<title>Security Architecture and DDS in about 10 minutes &#8211; looking forward to it! http:&#8230;</title>
		<link>http://www.facebook.com/MulticoreTech/posts/266979569999328</link>
		<comments>http://www.facebook.com/MulticoreTech/posts/266979569999328#comments</comments>
		<pubDate>Wed, 21 Sep 2011 14:51:34 +0000</pubDate>
		<dc:creator>Multicore TechChannel</dc:creator>
				<category><![CDATA[Blog]]></category>

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		<description><![CDATA[Security Architecture and DDS in about 10 minutes - looking forward to it! http://ow.ly/6AGJ9Event Registration (EVENT: 339257)ow.ly]]></description>
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		<title>Alcatel-Lucent tests &#064;Spirent 400G network processor http://ow.ly/6v8iO</title>
		<link>http://www.facebook.com/MulticoreTech/posts/264185760278709</link>
		<comments>http://www.facebook.com/MulticoreTech/posts/264185760278709#comments</comments>
		<pubDate>Thu, 15 Sep 2011 12:31:16 +0000</pubDate>
		<dc:creator>Multicore TechChannel</dc:creator>
				<category><![CDATA[Blog]]></category>

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		<description><![CDATA[Alcatel-Lucent tests &#064;Spirent 400G network processor http://ow.ly/6v8iO]]></description>
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		<title>Mike Demler reports on &quot;Package-Scale Power Management&quot; talks held at the 23rd a&#8230;</title>
		<link>http://www.facebook.com/MulticoreTech/posts/274735839208572</link>
		<comments>http://www.facebook.com/MulticoreTech/posts/274735839208572#comments</comments>
		<pubDate>Fri, 19 Aug 2011 16:13:23 +0000</pubDate>
		<dc:creator>Multicore TechChannel</dc:creator>
				<category><![CDATA[Blog]]></category>

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		<description><![CDATA[Mike Demler reports on &#34;Package-Scale Power Management&#34; talks held at the 23rd annual Hot Chips conference at Stanford UniversityEE Daily News: Hot Chips will need more analog to support multicorewww.eedailynews.com]]></description>
			<content:encoded><![CDATA[Mike Demler reports on &quot;Package-Scale Power Management&quot; talks held at the 23rd annual Hot Chips conference at Stanford University<br/><br/><a href="http://www.eedailynews.com/2011/08/hot-chips-will-need-more-analog-to.html" id="" title=""  onclick="" style="" onmousedown="UntrustedLink.bootstrap($(this), &quot;6AQHhUBgr&quot;, event, bagof(&#123;&#125;));" rel="nofollow"><img class="img" src="http://external.ak.fbcdn.net/safe_image.php?d=AQB9DMYYc7Wbu6ZC&amp;w=90&amp;h=90&amp;url=http%3A%2F%2F3.bp.blogspot.com%2F-qPbA161jyE8%2FTkyPWKRPIsI%2FAAAAAAAAAqQ%2FXm_r-bZznqY%2Fs72-c%2FScreenHunter_01%2BAug.%2B17%2B21.03.jpg" alt="" /></a><br/><a href="http://www.eedailynews.com/2011/08/hot-chips-will-need-more-analog-to.html" id=""  style="" onmousedown="UntrustedLink.bootstrap($(this), &quot;oAQFBCq3-&quot;, event, bagof(&#123;&#125;));" rel="nofollow">EE Daily News: Hot Chips will need more analog to support multicore</a><br/>www.eedailynews.com]]></content:encoded>
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		<title>Building universal connectivity</title>
		<link>http://embedded-computing.com/building-universal-connectivity</link>
		<comments>http://embedded-computing.com/building-universal-connectivity#comments</comments>
		<pubDate>Wed, 10 Aug 2011 15:00:00 +0000</pubDate>
		<dc:creator>Warren Webb, Editorial Director</dc:creator>
				<category><![CDATA[Blog]]></category>
		<category><![CDATA[Columns]]></category>
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		<category><![CDATA[best rtos]]></category>
		<category><![CDATA[cad software]]></category>
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		<category><![CDATA[electronics projects]]></category>
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		<category><![CDATA[Tracking Trends in Embedded Technology]]></category>
		<category><![CDATA[Universal connectivity]]></category>

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		<description><![CDATA[Warren's thoughts on the maturation of ubiquitous pervasive-computing, and an introduction to the Annual Resource Guide edition of Embedded Computing Design.]]></description>
			<content:encoded><![CDATA[<div
class="story"><span
id="more-465792"></span><span
class='body'><p
class="body-text-">As we approach the pervasive-computing vision, designers and customers alike are starting to expect universal connectivity in almost every embedded device. A ubiquitous network connection can enhance an <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20design">embedded design</a> in a number of ways, such as eliminating the hardware required for a local user interface or improving customer satisfaction with remote operation, software updates, troubleshooting, and automatic usage monitoring. Designers can also increase the apparent performance of an embedded product by offloading computing tasks to remote&nbsp;processors.</p><p
class="body-text-">A major challenge for embedded designers is to pick the appropriate connection mechanism depending on the product&#8217;s deployment location and <a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#security">security</a> requirements. Designers must choose from a wide range of networking interface standards, including Modbus or Ethernet for hardwired connections or Bluetooth, <a
rel="tag" href="http://tech.opensystemsmedia.com/smart-energy/#zigbee">ZigBee</a>, <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-wireless/#wi-fi">Wi-Fi</a>, and cellular for <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-wireless/#wireless">wireless</a> links.</p><p
class="body-text-">To ensure that these networking protocols track user requirements and match new applications, standards organizations are constantly updating and extending their offerings. For example, the Bluetooth Special Interest Group (SIG) recently released their version 4.0 specification that includes low energy Find&nbsp;Me and proximity profiles to locate or disable portable devices when they are separated from the authorized user by a specified distance. In addition to the obvious smartphone and laptop location tools, the Bluetooth SIG envisions new proximity-sensing applications that protect valuables, pets, and even children. It is easy to predict scores of new personal security products for the mass market based on this innovation.</p><p
class="body-text-">In this issue of <span
class="italics"><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20computing">Embedded Computing</a> Design</span>, we present a variety&nbsp;of technical content and opinions from experts in the embedded community. For example, Joachim Hallwachs of DesignArt Networks outlines the infrastructure changes that we can expect in data-centric networks, along with the role of a new generation of System-on-Chip (<a
rel="tag" href="http://channels.opensystemsmedia.com/SoC">SoC</a>) technology to simplify the transition. In the Silicon Q&amp;A section, Dr. &#216;yvind Str&#248;m of Atmel covers the latest ZigBee specifications and their use in low-power, <a
rel="tag" href="http://tech.opensystemsmedia.com/smart-energy/#smart%20energy">smart energy</a> embedded applications. In addition, Elie Ayache of Silicon Labs explains recent innovations and changes in timing components and how they will affect <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20designs">embedded designs</a>. Mitch Little of Microchip Technology also answers our questions about the technical challenges and future opportunities facing embedded design teams.</p><p
class="body-text-">In our Software section, Kim Hartman of TenAsys Corporation uncovers the price and performance implications of <a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/">virtualization</a><span
class="social" style="margin:0 0 0 3px">[<a
href="http://opsy.st/virtualization-facebook"><img
style="margin:0 2px -2px 2px;vertical-align:baseline" src="http://i.opensystemsmedia.com/i/a-facebook-12x12.gif" /></a>]</span> for real-time embedded applications employing <a
rel="tag" href="http://tech.opensystemsmedia.com/multicore/">multicore</a><span
class="social" style="margin:0 0 0 3px">[<a
href="http://opsy.st/multicore-facebook"><img
style="margin:0 2px -2px 2px;vertical-align:baseline" src="http://i.opensystemsmedia.com/i/a-facebook-12x12.gif" /></a>]</span> processor technology. He looks at techniques to combine a software platform requiring deterministic performance with a General-Purpose <a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#operating%20system">Operating System</a> (GPOS) for a <a
rel="tag" href="http://channels.opensystemsmedia.com/Gfx_Video">graphics</a>-rich user interface. In the same section, Ken Karnofsky of MathWorks answers a series of questions covering the fundamentals, trends, and advantages of employing <a
rel="tag" href="http://channels.opensystemsmedia.com/Model">model-based design</a> for embedded projects.</p><p
class="body-text-">The Strategies section of this issue includes an in-depth technical article by Johnson Yan of aJile Systems covering new innovations in <a
rel="tag" href="http://channels.opensystemsmedia.com/Java">Java</a> technology from the Open Services Gateway initiative (OSGi) Alliance tailored toward embedded devices. These innovations, along with new silicon-based platforms for direct Java bytecode execution, promise to enable Java-based systems that meet the performance, cost, and security requirements of today&#8217;s embedded devices. In a Strategies Q&amp;A session, Chuck&nbsp;Kostalnick of Avnet Embedded discloses that many of his customers are looking for off-the-shelf products to reduce schedules and avoid the costs of board layout, manufacturing, and <a
rel="tag" href="http://channels.opensystemsmedia.com/Obsolescence">life-cycle</a> management. Logic PD&#8217;s Mark Benson covers the <a
rel="tag" href="http://channels.opensystemsmedia.com/communications%20tech">radio frequency</a> emissions, security, and data integrity issues facing designers of wireless in-home <a
rel="tag" href="http://tech.opensystemsmedia.com/telehealth/">telehealth</a> devices.</p><p
class="body-text-">This issue also includes our annual Resource Guide, with a host of embedded products divided into dozens of categories to simplify your next design project. You can find wide-ranging off-the-shelf modules along with specialized embedded components to solve your unique requirements. You will also find plenty of embedded support software including OSs, development aids, and design automation tools.</p><p
class="body-text-">The articles, interviews, and product listings in this issue cover a broad section of the embedded industry that can serve as a valuable technical reference for your next project. Please give us your ideas on future topics and information that we can provide to support your design efforts. If you have an idea for a technical article that would be of interest to the embedded design community, please send me a short abstract.</p><p
class="body-text">Warren Webb, Editorial Director wwebb@opensystemsmedia.com</p></p></div><p></span></div></p><div
class="keywords"><h2>Topics covered in this article</h2><ul><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20design">embedded design</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-wireless/#wireless">wireless</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/safety-and-security/#security">security</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/smart-energy/#zigbee">zigbee</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-wireless/#wi-fi">wi-fi</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20computing">embedded computing</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#embedded%20designs">embedded designs</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/smart-energy/#smart%20energy">smart energy</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/SoC">SoC</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Model">Model-based design</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/embedded-software/#operating%20system">operating system</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/virtualization/">Virtualization</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/multicore/">multicore</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Gfx_Video">graphics</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/communications%20tech">radio frequency</a></li><li><a
rel="tag" href="http://tech.opensystemsmedia.com/telehealth/">telehealth</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Obsolescence">life-cycle</a></li><li><a
rel="tag" href="http://channels.opensystemsmedia.com/Java">Java</a></li></ul></div>]]></content:encoded>
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		<title>Multicore TechChannel&#8217;s Facebook Wall 2011-07-18 09:33:25</title>
		<link>http://www.facebook.com/permalink.php?story_fbid=235482756482343&#038;id=185780841452535</link>
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		<pubDate>Mon, 18 Jul 2011 16:33:25 +0000</pubDate>
		<dc:creator>Multicore TechChannel</dc:creator>
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		<description><![CDATA[E-cast: Migrate Network Equipment to Multi-Core with Virtualization]]></description>
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		<title>E-cast: Migrate Network Equipment to Multi-Core with Virtualization</title>
		<link>http://www.facebook.com/MulticoreTech/posts/235482756482343</link>
		<comments>http://www.facebook.com/MulticoreTech/posts/235482756482343#comments</comments>
		<pubDate>Mon, 18 Jul 2011 16:33:10 +0000</pubDate>
		<dc:creator>Multicore TechChannel</dc:creator>
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		<description><![CDATA[E-cast: Migrate Network Equipment to Multi-Core with Virtualization]]></description>
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		<title>Upcoming E-cast:  The MontaVista Approach to Multi-core SoC Resource Allocation&#8230;</title>
		<link>http://www.facebook.com/MulticoreTech/posts/174246212638740</link>
		<comments>http://www.facebook.com/MulticoreTech/posts/174246212638740#comments</comments>
		<pubDate>Wed, 06 Jul 2011 22:05:08 +0000</pubDate>
		<dc:creator>Multicore TechChannel</dc:creator>
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		<description><![CDATA[Upcoming E-cast:  The MontaVista Approach to Multi-core SoC Resource Allocation and Control (July 21st, 11am Eastern)The MontaVista Approach to Multi-core SoC Resource Allocation and Control Thursday, July 21, 2011 at 11:00am]]></description>
			<content:encoded><![CDATA[Upcoming E-cast:  The MontaVista Approach to Multi-core SoC Resource Allocation and Control (July 21st, 11am Eastern)<br/><br/><a href="http://www.facebook.com/events/227111857309624/" id="" title=""  onclick="" style=""><img class="img" src="http://profile.ak.fbcdn.net/static-ak/rsrc.php/v1/yy/r/XcB-JGXohjk.png" alt="" /></a><br/><a href="http://www.facebook.com/events/227111857309624/" id=""  style="">The MontaVista Approach to Multi-core SoC Resource Allocation and Control </a><br/>Thursday, July 21, 2011 at 11:00am]]></content:encoded>
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