Jul 2007 — By James Reinders
Multi-core chips from Intel and AMD offer a dramatic boost in speed and responsiveness, and plenty of opportunities for multiprocessing on ordinary desktop computers. But they also present a challenge: More than ever, multithreading is a requirement for good performance. This guide explains how to maximize the benefits of these processors through a portable C++ library that works on Windows, Linux, Macintosh, and Unix systems. With it, you'll learn how to use Intel Threading Building Blocks (TBB) effectively for parallel programming -- without having to be a threading expert.Enables you to specify tasks instead of threads for better portability, easier programming, more understandable source code, and better performance and scalability in generalFocuses on the goal of parallelizing computationally intensive work to deliver high-level solutionsIs compatible with other threading packages, and doesn't force you to pick one package for your entire programEmphasizes scalable, data-parallel programming, which allows program performance to increase as you add processorsRelies on generic programming, which enables you to write the best possible algorithms with the fewest constraintsAny C++ programmer who wants to write an application to run on a multi-core system will benefit from this book. TBB is also very approachable for a C programmer or a C++ programmer without much experience with templates. Best of all, you don't need experience with parallel programming or multi-core processors to use this book.
Written by James Reinders, Chief Evangelist of Intel Software Products, and based on the experience of Intel's developers and customers, this book explains the key tasks in multithreading and how to accomplish them with TBB in a portable and robust manner. With plenty of examples and full reference material, the book lays out common patterns of uses, reveals the gotchas in TBB, and gives important guidelines for choosing among alternatives in order to get the best performance.
You'll learn how Intel Threading Building Blocks:
Nov 2014 — By James Reinders and James Jeffers
High Performance Parallelism Pearls shows how to leverage parallelism on processors and coprocessors with the same programming – illustrating the most effective ways to better tap the computational potential of systems with Intel Xeon Phi coprocessors and Intel Xeon processors or other multicore processors. The book includes examples of successful programming efforts, drawn from across industries and domains such as chemistry, engineering, and environmental science. Each chapter in this edited work includes detailed explanations of the programming techniques used, while showing high performance results on both Intel Xeon Phi coprocessors and multicore processors. Learn from dozens of new examples and case studies illustrating "success stories" demonstrating not just the features of these powerful systems, but also how to leverage parallelism across these heterogeneous systems.Promotes consistent standards-based programming, showing in detail how to code for high performance on multicore processors and Intel® Xeon Phi™Examples from multiple vertical domains illustrating parallel optimizations to modernize real-world codesSource code available for download to facilitate further exploration
Feb 2010 — By André LaMothe
The Only Official Guide to the Parallax Multicore Propeller Microcontroller
Written by a team of Propeller experts, this authoritative guide shows you how to realize your design concepts by taking full advantage of the multicore Propeller microcontroller's unique architecture. The book begins with a review of the Propeller hardware, software, and Spin language so you can get started right away. Programming and Customizing the Multicore Propeller Microcontroller: The Official Guide is filled with a wide variety of step-by-step, hands-on projects. Put your ideas into production when you learn how to: Debug code for multiple cores Understand how the Propeller interacts with different sensors Wirelessly network Propeller chips Build a balancing robot and control it with computer vision Develop networking applications using an off-the-shelf Ethernet chip Create a portable multivariable GPS tracking and data logging device Use the Propeller as a remote virtual peripheral for media applications Create a Propeller-powered HVAC green house model Synthesize speech with the Propeller
Experience more of the process at mhprofessional.com/propeller
Memory Subsystem in Multicore Architectures: Design and analysis of a coherent memory subsystem for FPGA-based multicore embedded systemsNov 2014 — By Vahid RoostaieCache coherency and memory consistency are of the most decisive and challenging issues in the design of shared-memory multi-core systems that influence both the correctness and performance of parallel programs. In this book, we identify and analyze the problem of designing a coherent/consistent memory subsystem in general and then focus on FPGA-based multi-core embedded systems containing general purpose CPU's and dedicated hardware accelerators. We narrow down the range of the problem by targeting only the stream-based applications and developing dedicated application-specific solutions. A flexible Windowed-FIFO communication pattern is proposed to be used by the parallel programs being run on the multi-core system. The software APIs for the FPGA platform are implemented and tested, a customized streaming cache memory is designed, implemented and tested based on the proposed communication pattern and in the end, example embedded systems are developed and tested on the FPGA platform to prove the correct functionality of the APIs, the cache memory and the coherent data communication between the cores.
Apr 2013 — By Bryon Moyer and Editor
This Expert Guide gives you the techniques and technologies in embedded multicore to optimally design and implement your embedded system. Written by experts with a solutions focus, this encyclopedic reference gives you an indispensable aid to tackling the day-to-day problems when building and managing multicore embedded systems.
Following an embedded system design path from start to finish, our team of experts takes you from architecture, through hardware implementation to software programming and debug.
With this book you will learn:
• What motivates multicore
• The architectural options and tradeoffs; when to use what
• How to deal with the unique hardware challenges that multicore presents
• How to manage the software infrastructure in a multicore environment
• How to write effective multicore programs
• How to port legacy code into a multicore system and partition legacy software
• How to optimize both the system and software
• The particular challenges of debugging multicore hardware and softwareExamples demonstrating timeless implementation detailsProven and practical techniques reflecting the authors’ expertise built from years of experience and key advice on tackling critical issues
Nov 2015 — By Yan Solihin
Although multicore is now a mainstream architecture, there are few textbooks that cover parallel multicore architectures. Filling this gap, Fundamentals of Parallel Multicore Architecture provides all the material for a graduate or senior undergraduate course that focuses on the architecture of multicore processors. The book is also useful as a reference for professionals who deal with programming on multicore or designing multicore chips.
The text’s coverage of fundamental topics prepares students to study research papers in the multicore architecture area. The text offers many pedagogical features, including:Sufficiently short chapters that can be comfortably read over a weekend Introducing each concept by first describing the problem and building intuition that leads to the need for the concept "Did you know?" boxes that present mini case studies, alternative points of view, examples, and other interesting facts or discussion items Thought-provoking interviews with experts who share their perspectives on multicore architectures in the past, present, and future Online programming assignments and solutions that enhance students’ understanding
The first several chapters address programming issues in shared memory multiprocessors, such as the programming model and techniques to parallelize regular and irregular applications. The core of the book covers the architectures for shared memory multiprocessors. The final chapter contains interviews with experts in parallel multicore architecture.
Dec 2015 — By Robert Oshana
This book provides a set of practical processes and techniques used for multicore software development. It is written with a focus on solving day to day problems using practical tips and tricks and industry case studies to reinforce the key concepts in multicore software development.
The multicore landscape
Principles of parallel computing
Multicore SoC architectures
Multicore programming models
The Multicore development process
Multicore programming with threads
Concurrency abstraction layers
Debugging Multicore Systems
Practical techniques for getting started in multicore development
Case Studies in Multicore Systems Development
Sample code to reinforce many of the concepts discussed Presents the ‘nuts and bolts’ of programming a multicore systemProvides a short-format book on the practical processes and techniques used in multicore software developmentCovers practical tips, tricks and industry case studies to enhance the learning process
May 2014 — By Patrick Stakem
This book gives an overview of Multicore architectures, how they derive from multiprocessors, and illustrates the new applications they enable. A multicore processor has multiple cpu and memory elements in a single chip. Being on a single chip reduces the communications times between elements, and allows for multiprocessing. Advances in microelectronics fabrication techniques lead to the implementation of multicores for desktop and server machines around 2007. It was becoming increasingly difficult to increase clock speeds, so the obvious approach was to turn to parallelism. Currently, in this market, quad-core, 6-core, and 8-core chips are available. Besides additional cpu’s, additional on-chip memory must be added, usually in the form of memory caches, to keep the processors fed with instructions and data. There is no inherent difference in multicore architectures and multiprocessing with single core chips, except in the speed of communications. The standard interconnect technologies used in multiprocessing and clustering are applied to inter-core communications. Multicore technology is mainstream, and enables a vast application space.
Fuzzy Logic Based Power-Efficient Real-Time Multi-Core System (SpringerBriefs in Applied Sciences and Technology)Dec 2016 — By Jameel Ahmed, Mohammed Yakoob Siyal, Shaheryar Najam, and Zohaib Najam
This book focuses on identifying the performance challenges involved in computer architectures, optimal configuration settings and analysing their impact on the performance of multi-core architectures. Proposing a power and throughput-aware fuzzy-logic-based reconfiguration for Multi-Processor Systems on Chip (MPSoCs) in both simulation and real-time environments, it is divided into two major parts. The first part deals with the simulation-based power and throughput-aware fuzzy logic reconfiguration for multi-core architectures, presenting the results of a detailed analysis on the factors impacting the power consumption and performance of MPSoCs. In turn, the second part highlights the real-time implementation of fuzzy-logic-based power-efficient reconfigurable multi-core architectures for Intel and Leone3 processors.
Aug 2014 — By Jason Gregory
Hailed as a "must-have textbook" (CHOICE, January 2010), the first edition of Game Engine Architecture provided readers with a complete guide to the theory and practice of game engine software development. Updating the content to match today’s landscape of game engine architecture, this second edition continues to thoroughly cover the major components that make up a typical commercial game engine.
New to the Second Edition
Information on new topics, including the latest variant of the C++ programming language, C++11, and the architecture of the eighth generation of gaming consoles, the Xbox One and PlayStation 4 New chapter on audio technology covering the fundamentals of the physics, mathematics, and technology that go into creating an AAA game audio engine Updated sections on multicore programming, pipelined CPU architecture and optimization, localization, pseudovectors and Grassman algebra, dual quaternions, SIMD vector math, memory alignment, and anti-aliasing Insight into the making of Naughty Dog’s latest hit, The Last of Us
The book presents the theory underlying various subsystems that comprise a commercial game engine as well as the data structures, algorithms, and software interfaces that are typically used to implement them. It primarily focuses on the engine itself, including a host of low-level foundation systems, the rendering engine, the collision system, the physics simulation, character animation, and audio. An in-depth discussion on the "gameplay foundation layer" delves into the game’s object model, world editor, event system, and scripting system. The text also touches on some aspects of gameplay programming, including player mechanics, cameras, and AI.
An awareness-building tool and a jumping-off point for further learning, Game Engine Architecture, Second Edition gives readers a solid understanding of both the theory and common practices employed within each of the engineering disciplines covered. The book will help readers on their journey through this fascinating and multifaceted field.