Rugged Power // White paper
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White Paper: Enabling High-Speed Data Rates in Connectors for Aerospace and Defense Applications
A new high-speed connector system for aerospace and defense applications builds on industry-proven technology to achieve new levels of ruggedness. By combining the designs of cutting-edge high-speed connectors with proven MIL – SPEC contacts, the new Fortis Zd connector meets the demands of emerging military applications by enabling data rates of 10 Gb/s+ while performing in military-level vibration and shock conditions.
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eBook: Get Ready for 40G ATCA
In this eBook you will learn about the following: • What is driving the growth in IP traffic • The underlying technologies driving 40 Gbps ATCA • The relevant industry standards • The steps to 40G heaven
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White Paper: Lowering Power at 28 nm with Xilinx 7 Series FPGAs
This white paper describes several aspects of power related to the Xilinx(r) 28 nm 7 series FPGAs, including the TSMC 28 nm high-k metal gate (HKMG), high performance, low power (28 nm HPL or 28 HPL) process choice. The power benefits afforded by the 28 HPL process and its usefulness across Xilinx’s full product offerings is described as well as the architectural innovations and features for power reduction across the dimensions of static power, dynamic power, and I/O power.
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White Paper: Xilinx Redefines Power, Performance, and Design Productivity with Three Innovative 28 nm FPGA Families: Virtex-7, Kintex-7, and Artix-7 Devices
Industry dynamics are driving seemingly insatiable demand for higher bandwidth and higher system-level performance while facing more stringent mandatory requirements to reduce power consumption. At the same time, competitive pressures are forcing customers to increase productivity without sacrificing innovation and differentiation. To meet these demands, Xilinx(r) 7 series FPGAs leverage the unprecedented power, performance, and capacity enabled by TSMC’s 28 nm high-k metal gate (HKMG), high performance, low power (HPL) process technology and the unparalleled scalability afforded by the FPGA industry’s first unified silicon architecture to provide a comprehensive platform base for next-generation systems.
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White Paper: High-Volume Spartan-6 FPGAs: Performance and Power Performance and Power
The rapid change in today’s design environment requires a programmable solution that provides the highest performance and lowest power at the lowest cost. To meet the needs of high-volume systems, it is essential that the solution uses the latest 45 nm high-volume technology.
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White Paper: Reducing Switching Power with Intelligent Clock Gating
Xilinx delivers the first automated, fine-grain clock-gating solution that can reduce dynamic power by up to 30% in Virtex(r)-6, Spartan(r)-6, Kintex(tm)-7, and Virtex-7 FPGA designs. Xilinx intelligent clock-gating optimizations are automatically performed on the entire design, introduce no new tools or steps to the flow, and generate no changes to the existing logic or to the clocks that alter the behavior of the design. And, in most cases, the timing is also preserved.
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White Paper: Can You Have It All? Evaluating FPGA-Based Prototyping Systems
RTL simulation is no longer capable of providing all of the verification required for today’s complex designs. Modern systems are a complex mixture of hardware and software, digital and analog, and the boundaries of the system are often difficult to define.
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White Paper: No Room for Error: Creating Highly Reliable, High-Availability FPGA Designs
It comes as no surprise that the designers of FPGAs for military and aerospace applications are interested in increasing the reliability and availability of their designs. This is, of course, particularly true in the case of mission-critical and safety-critical electronic systems.
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White Paper: How Does the FMC (FPGA Mezzanine Card) Standard Measure up Against the PMC/XMC Format for Embedded Defense/Aerospace Applications?
FMCs promise to do for FPGA based solutions what PMC and XMC did for embedded CPU based systems. However, FMC is not really competing with PMC or XMC, but actually complements it, particularly for high bandwidth, low latency applications.
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White Paper: Design Approaches Impact GPGPU Implementation
The right choice for a GPGPU platform depends on several factors. Two approaches can be taken when implementing a GPGPU design: chip-down and mezzanine. GE Intelligent Platforms supports both design methods, allowing customers to choose the right approach for their program, including getting started with software design and system validation using early-access GPUs on MXMs, then migrating to chip-down designs later in the cycle when the program goes to production.
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White Paper: Addressing the Challenges of Functional Safety in the Automotive and Industrial Markets
The focus on safety-critical applications in both the automotive and industrial markets is significantly growing, bringing new and added pressures to systems engineers as they work to solve safety challenges.
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White Paper: Tips & Tricks for the professional use of PUE as a management tool
Used correctly, PUE metrics optimize the data center environment.